公开(公告)号：US10340906B2

公开(公告)日：2019-07-02

申请号：US15779432

申请日：2017-01-23

Applicant: SOUTHEAST UNIVERSITY ,  SOUTHEAST UNIVERSITY-WUXI INTEGRATED CIRCUIT TECHNOLOGY RESEARCH INSTITUTE

Inventor： Weifeng Sun ,  Yunwu Zhang ,  Kuo Yu ,  Jing Zhu ,  Shen Xu ,  Qinsong Qian ,  Siyang Liu ,  Shengli Lu ,  Longxing Shi

IPC: H02M3/07 ,  H03K17/06 ,  H03K17/16 ,  H03K17/687 ,  H03K19/0185 ,  H01L27/07 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10

Abstract: Parasitic high-voltage diodes implemented by integration technology in a high-voltage level shift circuit are used for charging a bootstrap capacitor CB, wherein a power supply end of the high voltage level shift circuit is a high-side floating power supply VB, and a reference ground is a floating voltage PGD that is controlled by a bootstrap control circuit. A first parasitic diode DB1 and a second parasitic diode DB2 are provided between the VB and the PGD. The bootstrap control circuit is controlled by a high-side signal and a low-side signal.

公开(公告)号：US12224340B2

公开(公告)日：2025-02-11

申请号：US17417663

申请日：2019-12-19

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Siyang Liu ,  Chi Zhang ,  Kui Xiao ,  Guipeng Sun ,  Dejin Wang ,  Jiaxing Wei ,  Li Lu ,  Weifeng Sun ,  Shengli Lu

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207

Abstract: A heterojunction semiconductor device with a low on-resistance includes a metal drain electrode, a substrate, and a buffer layer. A current blocking layer is arranged in the buffer layer, a gate structure is arranged on the buffer layer, and the gate structure comprises a metal gate electrode, GaN pillars and AlGaN layers, wherein a metal source electrode is arranged above the metal gate electrode; and the current blocking layer comprises multiple levels of current blocking layers, the centers of symmetry of the layers are collinear, and annular inner openings of the current blocking layers at all levels gradually become smaller from top to bottom. The AlGaN layers and the GaN pillars are distributed in a honeycomb above the buffer layer.

公开(公告)号：US11322606B2

公开(公告)日：2022-05-03

申请号：US16969437

申请日：2019-10-21

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng Sun ,  Siyang Liu ,  Sheng Li ,  Chi Zhang ,  Xinyi Tao ,  Ningbo Li ,  Longxing Shi

IPC: H01L29/778

Abstract: A heterojunction semiconductor device comprises a substrate; a second barrier layer is disposed on the second channel layer and a second channel is formed; a trench gate structure is disposed in the second barrier layer; the trench gate structure is embedded into the second barrier layer and is composed of a gate medium and a gate metal located in the gate medium; an isolation layer is disposed in the second channel layer and separates the second channel layer into an upper layer and a lower layer; a first barrier layer is disposed between the lower layer of the second channel layer and the first channel layer and a first channel is formed; a bottom of the metal drain is flush with a bottom of the first barrier layer; and a first metal source is disposed between the second metal source and the first channel layer.

公开(公告)号：US09159818B2

公开(公告)日：2015-10-13

申请号：US14349632

申请日：2012-10-24

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng Sun ,  Siyang Liu ,  Jing Zhu ,  Qinsong Qian ,  Shen Xu ,  Shengli Lu ,  Longxing Shi

IPC: H01L27/24 ,  H01L29/739 ,  H01L29/40 ,  H01L27/12 ,  H01L29/06 ,  H01L27/06

CPC classification number: H01L29/7394 ,  H01L27/0623 ,  H01L27/1203 ,  H01L29/0638 ,  H01L29/404

Abstract: A high-current, N-type silicon-on-insulator lateral insulated-gate bipolar transistor, including: a P-type substrate, a buried-oxide layer disposed on the P-type substrate, an N-type epitaxial layer disposed on the oxide layer, and an N-type buffer trap region. A P-type body region and an N-type central buffer trap region are disposed inside the N-type epitaxial layer; a P-type drain region is disposed in the buffer trap region; N-type source regions and a P-type body contact region are disposed in the P-type body region; an N-type base region and a P-type emitter region are disposed in the buffer trap region; gate and field oxide layers are disposed on the N-type epitaxial layer; polycrystalline silicon gates are disposed on the gate oxide layers; and a passivation layer and metal layers are disposed on the surface of the symmetrical transistor. P-type emitter region output and current density are improved without increasing the area of the transistor.

Abstract translation: 一种高电流，N型绝缘体上的横向绝缘栅双极晶体管，包括：P型衬底，设置在P型衬底上的掩埋氧化物层，设置在P型衬底上的N型外延层 氧化物层和N型缓冲阱捕获区。 P型体区域和N型中央缓冲区捕获区域设置在N型外延层内部; P型漏极区域设置在缓冲陷阱区域中; N型源极区域和P型体接触区域设置在P型体区域中; N型基极区域和P型发射极区域设置在缓冲陷阱区域中; 栅极和场氧化物层设置在N型外延层上; 多晶硅栅极设置在栅极氧化物层上; 并且钝化层和金属层设置在对称晶体管的表面上。 改善P型发射极区域的输出和电流密度，而不增加晶体管的面积。

公开(公告)号：US12046594B1

公开(公告)日：2024-07-23

申请号：US18638735

申请日：2024-04-18

Applicant: SOUTHEAST UNIVERSITY

Inventor： Long Zhang ,  Weifeng Sun ,  Siyang Liu ,  Chengwu Pan ,  Guiqiang Zheng ,  Longxing Shi

IPC: H01L27/06 ,  H01L23/528 ,  H01L29/20 ,  H01L29/778 ,  H01L29/8605 ,  H01L29/872 ,  H01L49/02 ,  H02M1/08

CPC classification number: H01L27/0605 ,  H01L23/5286 ,  H01L27/0629 ,  H01L27/0635 ,  H01L28/60 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/8605 ,  H01L29/872 ,  H02M1/08

Abstract: In the monolithically integrated GaN-based half-bridge circuit, a nucleation layer, a buffer layer, a channel layer and a barrier layer are sequentially provided on a conductive substrate, the barrier layer and the channel layer are separated by isolation layers, and a diode, an integrated capacitor, a low-side transistor, a high-side transistor, a first integrated resistor and a second integrated resistor are provided. The half-bridge circuit includes: a low-side transistor and a high-side transistor, wherein a drain of the low-side transistor is connected to a source of the high-side transistor and also connected to an output terminal Vout, and a substrate of the low-side transistor is connected to a substrate of the high-side transistor, wherein a series resistor is connected in parallel to a drain of the high-side transistor and a source of the low-side transistor.

公开(公告)号：US11158708B1

公开(公告)日：2021-10-26

申请号：US16486494

申请日：2018-09-25

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng Sun ,  Siyang Liu ,  Lizhi Tang ,  Sheng Li ,  Chi Zhang ,  Jiaxing Wei ,  Shengli Lu ,  Longxing Shi

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/06

Abstract: The invention provides a graphene channel silicon carbide power semiconductor transistor, and its cellular structure thereof. Characterized in that, a graphene strip serving as a channel is embedded in a surface of the P-type body region and two ends of the graphene strip are respectively contacted with a boundary between the N+-type source region and the P-type body region and a boundary between the P-type body region and the N-type drift region, and the graphene strip is distributed in a cellular manner in a gate width direction, a conducting channel of a device is still made of graphene; in the case of maintaining basically invariable on-resistance and current transmission capacity, the P-type body regions are separated by the graphene strip, thus enhancing a function of assisting depletion, which further reduces an overall off-state leakage current of the device, and improves a breakdown voltage.

公开(公告)号：US20150270377A1

公开(公告)日：2015-09-24

申请号：US14439715

申请日：2012-12-27

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng Sun ,  Jing Zhu ,  Shen Xu ,  Qinsong Qian ,  Siyang Liu ,  Shengli Lu ,  Longxing Shi

IPC: H01L29/739 ,  H01L23/528 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L29/7394 ,  H01L23/528 ,  H01L29/0611 ,  H01L29/0696 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/1008 ,  H01L29/4916 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transverse ultra-thin insulated gate bipolar transistor having current density includes: a P substrate, where the P substrate is provided with a buried oxide layer thereon, the buried oxide layer is provided with an N epitaxial layer thereon, the N epitaxial layer is provided with an N well region and P base region therein, the P base region is provided with a first P contact region and an N source region therein, the N well region is provided with an N buffer region therein, the N well region is provided with a field oxide layer thereon, the N buffer region is provided with a P drain region therein, the N epitaxial layer is provided therein with a P base region array including a P annular base region, the P base region array is located between the N well region and the P base region, the P annular base region is provided with a second P contact region and an N annular source region therein, and the second P contact region is located in the N annular source region. The present invention greatly increases current density of a transverse ultra-thin insulated gate bipolar transistor, thus significantly improving the performance of an intelligent power module.

Abstract translation: 具有电流密度的横向超薄绝缘栅双极晶体管包括：P基板，其中P基板在其上设置有掩埋氧化物层，所述掩埋氧化物层在其上设置有N外延层，提供N外延层 在其中具有N阱区域和P基极区域，P基极区域中设置有第一P接触区域和N源极区域，N阱区域中设置有N个缓冲区域，N阱区域设置有 在其上的场氧化物层，N缓冲区在其中设置有P漏极区，N外延层中设置有包括P环状基极区的P基区阵列，P基区阵列位于N阱之间 区域和P基区域中，P环状基部区域设置有第二P接触区域和N环状源极区域，第二P接触区域位于N环状源极区域中。 本发明大大增加了横向超薄绝缘栅双极晶体管的电流密度，从而显着提高了智能功率模块的性能。

公开(公告)号：US12107167B2

公开(公告)日：2024-10-01

申请号：US17762929

申请日：2021-01-20

Applicant: SOUTHEAST UNIVERSITY

Inventor： Siyang Liu ,  Weifeng Sun ,  Chi Zhang ,  Shuxuan Xin ,  Shen Li ,  Le Qian ,  Chen Ge ,  Longxing Shi

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/778 ,  H01L29/812

CPC classification number: H01L29/7851 ,  H01L29/1095 ,  H01L29/778 ,  H01L29/8122

Abstract: The present invention discloses a high-threshold power semiconductor device and a manufacturing method thereof. The high-threshold power semiconductor device includes, in sequence from bottom to top: a metal drain electrode, a substrate, a buffer layer, and a drift region; further including: a composite column body which is jointly formed by a drift region protrusion, a columnar p-region and a columnar n-region on the drift region, a channel layer, a passivation layer, a dielectric layer, a heavily doped semiconductor layer, a metal gate electrode and a source metal electrode. The composite column body is formed by sequentially depositing a p-type semiconductor layer and an n-type semiconductor layer on the drift region and then etching same. The channel layer and the passivation layer are formed in sequence by deposition. Thus, the above devices are divided into a cell region and a terminal region. The dielectric layer, the heavily doped semiconductor layer, the metal gate electrode and the source metal electrode only exist in the cell region, and the passivation layer of the terminal region extends upwards and is wrapped outside the channel layer. This structure can increase a threshold voltage of the device, improve the blocking characteristics of the device and reduce the size of a gate capacitance.

公开(公告)号：US09240469B2

公开(公告)日：2016-01-19

申请号：US14439715

申请日：2012-12-27

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng Sun ,  Jing Zhu ,  Shen Xu ,  Qinsong Qian ,  Siyang Liu ,  Shengli Lu ,  Longxing Shi

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/49 ,  H01L29/10 ,  H01L29/08 ,  H01L23/528

CPC classification number: H01L29/7394 ,  H01L23/528 ,  H01L29/0611 ,  H01L29/0696 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/1008 ,  H01L29/4916 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transverse ultra-thin insulated gate bipolar transistor having current density includes: a P substrate, where the P substrate is provided with a buried oxide layer thereon, the buried oxide layer is provided with an N epitaxial layer thereon, the N epitaxial layer is provided with an N well region and P base region therein, the P base region is provided with a first P contact region and an N source region therein, the N well region is provided with an N buffer region therein, the N well region is provided with a field oxide layer thereon, the N buffer region is provided with a P drain region therein, the N epitaxial layer is provided therein with a P base region array including a P annular base region, the P base region array is located between the N well region and the P base region, the P annular base region is provided with a second P contact region and an N annular source region therein, and the second P contact region is located in the N annular source region. The present invention greatly increases current density of a transverse ultra-thin insulated gate bipolar transistor, thus significantly improving the performance of an intelligent power module.

Abstract translation: 具有电流密度的横向超薄绝缘栅双极晶体管包括：P基板，其中P基板在其上设置有掩埋氧化物层，所述掩埋氧化物层在其上设置有N外延层，提供N外延层 在其中具有N阱区域和P基极区域，P基极区域中设置有第一P接触区域和N源极区域，N阱区域中设置有N个缓冲区域，N阱区域设置有 在其上的场氧化物层，N缓冲区在其中设置有P漏极区，N外延层中设置有包括P环状基极区的P基区阵列，P基区阵列位于N阱之间 区域和P基区域中，P环状基部区域设置有第二P接触区域和N环状源极区域，第二P接触区域位于N环状源极区域中。 本发明大大增加了横向超薄绝缘栅双极晶体管的电流密度，从而显着提高了智能功率模块的性能。

公开(公告)号：US12183818B2

公开(公告)日：2024-12-31

申请号：US17417677

申请日：2019-12-23

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Weifeng Sun ,  Rongcheng Lou ,  Kui Xiao ,  Feng Lin ,  Jiaxing Wei ,  Sheng Li ,  Siyang Liu ,  Shengli Lu ,  Longxing Shi

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66

Abstract: A power semiconductor device includes: a substrate; drain metal; a drift region; a base region; a gate structure; a first conductive type doped region contacting the base region on the side of the base region distant from the gate structure; a source region provided in the base region and between the first conductive type doped region and the gate structure; contact metal that is provided on the first conductive type doped region and forms a contact barrier having rectifying characteristics together with the first conductive type doped region below; and source metal wrapping the contact metal and contacting the source region.