公开(公告)号：US12027516B1

公开(公告)日：2024-07-02

申请号：US18568277

申请日：2022-12-29

Applicant: SOUTHEAST UNIVERSITY

Inventor： Siyang Liu ,  Sheng Li ,  Chi Zhang ,  Weifeng Sun ,  Mengli Liu ,  Yanfeng Ma ,  Longxing Shi

IPC: H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/7787

Abstract: A GaN power semiconductor device integrated with a self-feedback gate control structure comprises a substrate, a buffer layer, a channel layer and a barrier layer. A gate control area is formed by a first metal source electrode, a first P-type GaN cap layer, a first metal gate electrode, a first metal drain electrode, a second P-type GaN cap layer and a second metal gate electrode. An active working area is formed by the first metal source electrode, a third P-type GaN cap layer, a third metal gate electrode, a second metal drain electrode, the second P-type GaN cap layer and a second metal source electrode. The overall gate leaking current of the device is regulated by the gate control area, the integration level is high, the parasitic effect is small, and the charge-storage effect can be effectively relieved, thus improving the threshold stability of the device.

公开(公告)号：US11515395B2

公开(公告)日：2022-11-29

申请号：US17624336

申请日：2020-09-25

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD

Inventor： Siyang Liu ,  Ningbo Li ,  Dejin Wang ,  Kui Xiao ,  Chi Zhang ,  Sheng Li ,  Xinyi Tao ,  Weifeng Sun ,  Longxing Shi

IPC: H01L29/872 ,  H01L29/20 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/861

Abstract: A gallium nitride power device, including: a gallium nitride substrate; cathodes; a plurality of gallium nitride protruding structures arranged on the gallium nitride substrate and between the cathodes, a groove is formed between adjacent gallium nitride protruding structures; an electron transport layer, covering a top portion and side surfaces of each of the gallium nitride protruding structures; a gallium nitride layer, arranged on the electron transport layer and filling each of the grooves; a plurality of second conductivity type regions, where each of the second conductivity type regions extends downward from a top portion of the gallium nitride layer into one of the grooves, and the top portion of each of the gallium nitride protruding structures is higher than a bottom portion of each of the second conductivity type regions; and an anode, arranged on the gallium nitride layer and the second conductivity type regions.

公开(公告)号：US11158708B1

公开(公告)日：2021-10-26

申请号：US16486494

申请日：2018-09-25

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng Sun ,  Siyang Liu ,  Lizhi Tang ,  Sheng Li ,  Chi Zhang ,  Jiaxing Wei ,  Shengli Lu ,  Longxing Shi

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/06

Abstract: The invention provides a graphene channel silicon carbide power semiconductor transistor, and its cellular structure thereof. Characterized in that, a graphene strip serving as a channel is embedded in a surface of the P-type body region and two ends of the graphene strip are respectively contacted with a boundary between the N+-type source region and the P-type body region and a boundary between the P-type body region and the N-type drift region, and the graphene strip is distributed in a cellular manner in a gate width direction, a conducting channel of a device is still made of graphene; in the case of maintaining basically invariable on-resistance and current transmission capacity, the P-type body regions are separated by the graphene strip, thus enhancing a function of assisting depletion, which further reduces an overall off-state leakage current of the device, and improves a breakdown voltage.

公开(公告)号：US12224340B2

公开(公告)日：2025-02-11

申请号：US17417663

申请日：2019-12-19

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Siyang Liu ,  Chi Zhang ,  Kui Xiao ,  Guipeng Sun ,  Dejin Wang ,  Jiaxing Wei ,  Li Lu ,  Weifeng Sun ,  Shengli Lu

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207

Abstract: A heterojunction semiconductor device with a low on-resistance includes a metal drain electrode, a substrate, and a buffer layer. A current blocking layer is arranged in the buffer layer, a gate structure is arranged on the buffer layer, and the gate structure comprises a metal gate electrode, GaN pillars and AlGaN layers, wherein a metal source electrode is arranged above the metal gate electrode; and the current blocking layer comprises multiple levels of current blocking layers, the centers of symmetry of the layers are collinear, and annular inner openings of the current blocking layers at all levels gradually become smaller from top to bottom. The AlGaN layers and the GaN pillars are distributed in a honeycomb above the buffer layer.

公开(公告)号：US11322606B2

公开(公告)日：2022-05-03

申请号：US16969437

申请日：2019-10-21

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng Sun ,  Siyang Liu ,  Sheng Li ,  Chi Zhang ,  Xinyi Tao ,  Ningbo Li ,  Longxing Shi

IPC: H01L29/778

Abstract: A heterojunction semiconductor device comprises a substrate; a second barrier layer is disposed on the second channel layer and a second channel is formed; a trench gate structure is disposed in the second barrier layer; the trench gate structure is embedded into the second barrier layer and is composed of a gate medium and a gate metal located in the gate medium; an isolation layer is disposed in the second channel layer and separates the second channel layer into an upper layer and a lower layer; a first barrier layer is disposed between the lower layer of the second channel layer and the first channel layer and a first channel is formed; a bottom of the metal drain is flush with a bottom of the first barrier layer; and a first metal source is disposed between the second metal source and the first channel layer.

公开(公告)号：US12107167B2

公开(公告)日：2024-10-01

申请号：US17762929

申请日：2021-01-20

Applicant: SOUTHEAST UNIVERSITY

Inventor： Siyang Liu ,  Weifeng Sun ,  Chi Zhang ,  Shuxuan Xin ,  Shen Li ,  Le Qian ,  Chen Ge ,  Longxing Shi

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/778 ,  H01L29/812

CPC classification number: H01L29/7851 ,  H01L29/1095 ,  H01L29/778 ,  H01L29/8122

Abstract: The present invention discloses a high-threshold power semiconductor device and a manufacturing method thereof. The high-threshold power semiconductor device includes, in sequence from bottom to top: a metal drain electrode, a substrate, a buffer layer, and a drift region; further including: a composite column body which is jointly formed by a drift region protrusion, a columnar p-region and a columnar n-region on the drift region, a channel layer, a passivation layer, a dielectric layer, a heavily doped semiconductor layer, a metal gate electrode and a source metal electrode. The composite column body is formed by sequentially depositing a p-type semiconductor layer and an n-type semiconductor layer on the drift region and then etching same. The channel layer and the passivation layer are formed in sequence by deposition. Thus, the above devices are divided into a cell region and a terminal region. The dielectric layer, the heavily doped semiconductor layer, the metal gate electrode and the source metal electrode only exist in the cell region, and the passivation layer of the terminal region extends upwards and is wrapped outside the channel layer. This structure can increase a threshold voltage of the device, improve the blocking characteristics of the device and reduce the size of a gate capacitance.