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公开(公告)号：US20240321789A1
公开(公告)日：2024-09-26
申请号：US18458109
申请日：2023-08-29
Inventor： Kazuyuki HIGASHI , Kei OBARA , Kazumichi TSUMURA
IPC: H01L23/00 , H01L25/065
CPC classification number: H01L24/05 , H01L24/13 , H01L25/0657 , H01L2224/0401 , H01L2224/05011 , H01L2224/05082 , H01L2224/05166 , H01L2224/05551 , H01L2224/05573 , H01L2224/05664 , H01L2224/05666 , H01L2224/13019 , H01L2224/13022 , H01L2224/13026 , H01L2224/13144 , H01L2225/06513
Abstract: A bonding-type interconnection member includes a first substrate; a first interconnection portion stacked on the first substrate and including a first insulating layer, a first interconnection layer, and a first connection hole reaching the first interconnection layer; a second substrate facing the first interconnection portion in a first direction; a bonding metal portion provided between the first connection hole and the second substrate; a first conductive film provided in the first connection hole and in contact with the first interconnection layer on a bottom surface of the first connection hole; and a second conductive film provided between the first conductive film and the bonding metal portion, and in contact with the first conductive film and the bonding metal portion. The first conductive film is made of a material different from a material of the second conductive film and a material of the bonding metal portion.
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公开(公告)号：US20240014159A1
公开(公告)日：2024-01-11
申请号：US18471358
申请日：2023-09-21
Applicant: ROHM CO., LTD.
Inventor： Bungo TANAKA , Keiji WADA , Satoshi KAGEYAMA
IPC: H01L23/00 , H01L23/31 , H01L23/522 , H01L23/495 , H01L23/528
CPC classification number: H01L24/13 , H01L23/3114 , H01L24/05 , H01L23/5226 , H01L23/49548 , H01L23/5283 , H01L23/49582 , H01L24/06 , H01L24/03 , H01L2924/01046 , H01L24/48 , H01L2224/04042 , H01L2224/13147 , H01L2224/1357 , H01L2224/13647 , H01L2224/13018 , H01L2224/13082 , H01L2224/13166 , H01L2224/13181 , H01L2224/13184 , H01L2224/1318 , H01L2224/13176 , H01L2224/13171 , H01L2224/05582 , H01L2224/05655 , H01L2224/05664 , H01L2224/48091 , H01L2224/48227 , H01L2924/01029 , H01L2924/01022 , H01L2924/04941 , H01L2924/01073 , H01L2924/01074 , H01L2924/01042 , H01L2924/01024 , H01L2924/01044 , H01L2924/01028 , H01L24/83 , H01L24/32 , H01L2224/83801 , H01L2224/05147 , H01L2224/48465 , H01L24/73 , H01L24/29 , H01L23/562 , H01L2224/29101 , H01L2224/05012 , H01L2224/45124 , H01L2224/73265 , H01L2224/45144 , H01L2924/181 , H01L23/53223
Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.
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公开(公告)号：US11824047B2
公开(公告)日：2023-11-21
申请号：US17993248
申请日：2022-11-23
Applicant: NANYA TECHNOLOGY CORPORATION
Inventor： Tse-Yao Huang
IPC: H01L25/065 , H01L25/18 , H01L25/00 , H01L23/00 , H01L23/31 , H01L21/768 , H01L21/02 , H01L23/532
CPC classification number: H01L25/0657 , H01L21/76898 , H01L23/3171 , H01L24/06 , H01L24/08 , H01L24/80 , H01L25/18 , H01L25/50 , H01L21/02063 , H01L21/02274 , H01L23/5329 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/83 , H01L24/92 , H01L2224/0345 , H01L2224/03462 , H01L2224/03831 , H01L2224/05155 , H01L2224/05624 , H01L2224/05647 , H01L2224/05657 , H01L2224/05664 , H01L2224/06181 , H01L2224/08145 , H01L2224/08146 , H01L2224/13025 , H01L2224/16146 , H01L2224/80203 , H01L2224/83203 , H01L2224/9211 , H01L2225/06513 , H01L2225/06544
Abstract: The present application provides a method for fabricating a semiconductor device including providing a first semiconductor die including a first substrate including a first substrate including a first region and a second region, a plurality of first through substrate vias in the first region, a first circuit layer on the first substrate, and a control circuit on the first region and in the first circuit layer; forming a plurality of through die vias vertically along the first circuit layer and the second region; providing a second semiconductor die including a plurality of second conductive pads substantially coplanar with a top surface of the second semiconductor die; providing a third semiconductor die including a plurality of third conductive pads substantially coplanar with a top surface of the third semiconductor die; flipping the second semiconductor die and bonding the second semiconductor die onto the first circuit layer.
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公开(公告)号：US11764752B2
公开(公告)日：2023-09-19
申请号：US16218526
申请日：2018-12-13
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Masatoshi Nakagawa
CPC classification number: H03H9/02905 , H01L24/05 , H01L24/97 , H03H9/02834 , H03H9/02866 , H03H9/059 , H03H9/1085 , H01L24/13 , H01L24/16 , H01L2224/0568 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/05671 , H01L2224/05684 , H01L2224/13101 , H01L2224/13144 , H01L2224/81444 , H01L2224/97 , H01L2924/01013 , H01L2924/10157 , H01L2924/181 , H01L2924/3511 , H01L2924/3511 , H01L2924/00 , H01L2224/05624 , H01L2924/00014 , H01L2224/05647 , H01L2924/00014 , H01L2224/05669 , H01L2924/00014 , H01L2224/05644 , H01L2924/00014 , H01L2224/05639 , H01L2924/00014 , H01L2224/05664 , H01L2924/00014 , H01L2224/05666 , H01L2924/00014 , H01L2224/05655 , H01L2924/00014 , H01L2224/05671 , H01L2924/00014 , H01L2224/0568 , H01L2924/00014 , H01L2224/05684 , H01L2924/00014 , H01L2224/81444 , H01L2924/00014 , H01L2224/13144 , H01L2924/00014 , H01L2224/13101 , H01L2924/014 , H01L2924/00014 , H01L2924/181 , H01L2924/00012
Abstract: An elastic wave device includes an elastic wave element chip, a bump electrically connected to the elastic wave element chip, a package substrate including an electrode bonded to the bump, the elastic wave element chip mounted on the package substrate with the bump, and a sealing resin portion covering the elastic wave element chip on the package substrate. A space surrounded by the elastic wave element chip, the package substrate, and the sealing resin portion is provided. The elastic wave element chip includes a substrate having piezoelectricity, an interdigital transducer electrode, and a pad electrode. A first main surface of the substrate having piezoelectricity includes a first region and a second region closer to a second main surface than the first region. The interdigital transducer electrode is disposed in the first region. The pad electrode is disposed in the second region and bonded to the bump.
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公开(公告)号：US20230197657A1
公开(公告)日：2023-06-22
申请号：US17555987
申请日：2021-12-20
Applicant: International Business Machines Corporation
Inventor： Katsuyuki Sakuma , Mukta Ghate Farooq
IPC: H01L23/00
CPC classification number: H01L24/13 , H01L24/16 , H01L24/81 , H01L24/05 , H01L2224/16145 , H01L2224/1601 , H01L2224/1308 , H01L2224/13147 , H01L2224/13144 , H01L2224/13164 , H01L2224/13155 , H01L2224/81815 , H01L2224/05644 , H01L2224/05664 , H01L2224/05647 , H01L2224/05655
Abstract: A semiconductor device and formation thereof. The semiconductor device includes a first semiconductor structure, a second semiconductor structure, and a plurality of pillars interconnecting the first semiconductor structure and the second semiconductor structure. The plurality of pillars include a first solder layer and a second solder layer, wherein the first solder layer has a higher melting point than the second solder layer.
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6.发明申请
公开(公告)号：US20190237434A1
公开(公告)日：2019-08-01
申请号：US16377558
申请日：2019-04-08
Applicant: Micron Technology, Inc.
Inventor： Jaspreet S. Gandhi
IPC: H01L25/065 , H01L23/00 , H01L25/00 , H01L25/18
CPC classification number: H01L25/0657 , H01L24/02 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/18 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/05025 , H01L2224/05155 , H01L2224/05548 , H01L2224/05567 , H01L2224/05582 , H01L2224/05664 , H01L2224/06181 , H01L2224/11334 , H01L2224/11462 , H01L2224/11464 , H01L2224/13022 , H01L2224/13024 , H01L2224/13025 , H01L2224/13083 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/13541 , H01L2224/13564 , H01L2224/13582 , H01L2224/13611 , H01L2224/13655 , H01L2224/13664 , H01L2224/1403 , H01L2224/14181 , H01L2224/16058 , H01L2224/16145 , H01L2224/16146 , H01L2224/16148 , H01L2224/16227 , H01L2224/16503 , H01L2224/17181 , H01L2224/32145 , H01L2224/73204 , H01L2224/81191 , H01L2224/81203 , H01L2224/81801 , H01L2224/8181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2924/00 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01327 , H01L2924/014 , H01L2924/1431 , H01L2924/1434 , H01L2924/1436 , H01L2924/3512 , H01L2924/00014
Abstract: Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, an interconnect structure includes a first conductive element, a second conductive element, and an intermetallic palladium joint. The intermetallic palladium joint includes an intermetallic crystallite spanning between the first and second conductive elements. The intermetallic crystallite includes a first end portion and a second end portion. The first end portion directly contacts the first conductive element. The second end portion directly contacts the second conductive element.
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公开(公告)号：US20190206841A1
公开(公告)日：2019-07-04
申请号：US16106521
申请日：2018-08-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Young Lyong KIM , Seung Duk BAEK
IPC: H01L25/065 , H01L23/00 , H01L23/31
CPC classification number: H01L25/0657 , H01L21/561 , H01L23/291 , H01L23/293 , H01L23/3128 , H01L23/3135 , H01L23/3171 , H01L23/3192 , H01L23/481 , H01L23/5383 , H01L24/05 , H01L24/09 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/94 , H01L25/0652 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/05022 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05169 , H01L2224/05184 , H01L2224/05567 , H01L2224/05568 , H01L2224/0557 , H01L2224/05573 , H01L2224/0558 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/05671 , H01L2224/05684 , H01L2224/06181 , H01L2224/08145 , H01L2224/09181 , H01L2224/13007 , H01L2224/13017 , H01L2224/13021 , H01L2224/13022 , H01L2224/13082 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13118 , H01L2224/1312 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/13164 , H01L2224/13169 , H01L2224/16146 , H01L2224/16147 , H01L2224/16148 , H01L2224/16237 , H01L2224/17181 , H01L2224/73204 , H01L2224/81005 , H01L2224/81191 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2924/014 , H01L2924/013 , H01L2924/01082 , H01L2924/01047 , H01L2924/01079 , H01L2924/01029 , H01L2924/01083 , H01L2924/0103 , H01L2924/01074 , H01L2924/01023 , H01L2224/03 , H01L2224/11 , H01L2224/81
Abstract: A semiconductor package includes a first semiconductor chip having a first chip substrate, the first chip substrate having a first upper surface and a first lower surface opposite to each other, a first through-silicon via (TSV), a lower connection pad and a first lower passivation layer on the first lower surface of the first chip substrate, the first lower passivation layer exposing a portion of the lower connection pad, an upper connection pad and a first upper passivation layer on the first upper surface of the first chip substrate, the first upper passivation layer including a first upper inorganic material layer, and a second semiconductor chip connected to the first semiconductor chip, the second semiconductor chip including a second TSV, wherein the first lower passivation layer has a stacked structure of a first lower inorganic material layer and a lower organic material layer.
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公开(公告)号：US20190027455A1
公开(公告)日：2019-01-24
申请号：US16137683
申请日：2018-09-21
Applicant: Renesas Electronics Corporation
Inventor： SHINYA SUZUKI , Kiichi Makuta
IPC: H01L23/00 , H01L23/522 , H01L23/528 , H01L27/02 , H01L23/498
CPC classification number: H01L24/17 , G02F1/13306 , G02F1/13452 , H01L23/49811 , H01L23/5226 , H01L23/528 , H01L23/53209 , H01L23/53214 , H01L23/53238 , H01L23/5329 , H01L24/10 , H01L24/13 , H01L24/14 , H01L27/0207 , H01L27/0248 , H01L27/0255 , H01L27/0292 , H01L2224/05124 , H01L2224/05166 , H01L2224/05184 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/13 , H01L2224/13099 , H01L2224/13144 , H01L2224/13644 , H01L2224/1403 , H01L2224/1412 , H01L2224/16 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/81191 , H01L2224/9211 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01025 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01055 , H01L2924/01057 , H01L2924/01059 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/013 , H01L2924/04941 , H01L2924/10161 , H01L2924/14 , H01L2924/1426 , H01L2924/15788 , H01L2924/30105 , H01L2924/00 , H01L2924/00014
Abstract: To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.
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公开(公告)号：US10037962B2
公开(公告)日：2018-07-31
申请号：US15584498
申请日：2017-05-02
Inventor： Tsung-Yuan Yu , Hsien-Wei Chen , Jie Chen
IPC: H01L23/00 , H01L23/544 , H01L23/13 , H05K1/11 , H05K3/34
CPC classification number: H01L24/17 , H01L23/13 , H01L23/147 , H01L23/49816 , H01L23/49833 , H01L23/544 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L2223/54426 , H01L2224/0345 , H01L2224/04 , H01L2224/0401 , H01L2224/05001 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05184 , H01L2224/05551 , H01L2224/05559 , H01L2224/05568 , H01L2224/05572 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05671 , H01L2224/05681 , H01L2224/05684 , H01L2224/11 , H01L2224/11334 , H01L2224/1146 , H01L2224/11849 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/16238 , H01L2224/1705 , H01L2224/32225 , H01L2224/73204 , H01L2224/81007 , H01L2224/8114 , H01L2224/81191 , H01L2224/81193 , H01L2224/81365 , H01L2224/81815 , H01L2224/92125 , H01L2225/1058 , H01L2924/00014 , H01L2924/10253 , H01L2924/10271 , H01L2924/10272 , H01L2924/10329 , H05K1/111 , H05K3/3436 , H05K2201/09036 , H05K2201/10674 , H05K2201/10734 , H01L2924/014 , H01L2224/05552
Abstract: A package includes a first package component, a second package component over the first package component, and a solder region bonding the first package component to the second package component. At least one ball-height control stud separates the first package component and the second package component from each other, and defines a standoff distance between the first package component and the second package component.
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公开(公告)号：US09966348B2
公开(公告)日：2018-05-08
申请号：US15716534
申请日：2017-09-27
Applicant: Infineon Technologies AG
Inventor： Jens Peter Konrath , Jochen Hilsenbeck
CPC classification number: H01L24/03 , B81C1/00 , H01L24/05 , H01L24/06 , H01L29/40 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/03612 , H01L2224/03614 , H01L2224/0381 , H01L2224/0383 , H01L2224/0391 , H01L2224/05017 , H01L2224/05025 , H01L2224/05155 , H01L2224/05166 , H01L2224/05557 , H01L2224/05558 , H01L2224/05582 , H01L2224/05601 , H01L2224/05613 , H01L2224/05624 , H01L2224/05638 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05663 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/05673 , H01L2224/06181 , H01L2924/01029 , H01L2924/01014 , H01L2924/00012 , H01L2924/00014 , H01L2924/01076 , H01L2924/0108
Abstract: According to various embodiments an electronic component includes: at least one electrically conductive contact region; a contact pad including a self-segregating composition disposed over the at least one electrically conductive contact region; a segregation suppression structure disposed between the contact pad and the at least one electrically conductive contact region, wherein the segregation suppression structure includes more nucleation inducing topography features than the at least one electrically conductive contact region for perturbing a chemical segregation of the self-segregating composition by crystallographic interfaces of the contact pad defined by the nucleation inducing topography features.
