公开(公告)号：US20170212167A1

公开(公告)日：2017-07-27

申请号：US15481891

申请日：2017-04-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Cheng Wu ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Chen-Hua Yu ,  Chao-Hsiang Yang

IPC分类号： G01R31/28 ,  G01R1/04 ,  H01L23/00 ,  G01R31/26

CPC分类号： G01R31/2896 ,  G01R1/0416 ,  G01R31/2601 ,  G01R31/2884 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02377 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/0614 ,  H01L2224/0616 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16238 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014

摘要： A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.

公开(公告)号：US09618572B2

公开(公告)日：2017-04-11

申请号：US15170062

申请日：2016-06-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Cheng Wu ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Chen-Hua Yu ,  Chao-Hsiang Yang

IPC分类号： H01R31/00 ,  G01R31/28 ,  H01L21/66 ,  G01R1/04 ,  G01R31/26 ,  H01L23/00

CPC分类号： G01R31/2896 ,  G01R1/0416 ,  G01R31/2601 ,  G01R31/2884 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02377 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/0614 ,  H01L2224/0616 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16238 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014

摘要： A package includes a semiconductor chip. The semiconductor chip includes a test pad, and a plurality of microbump pads, wherein each microbump pad of the plurality of microbump pads is electrically connected to the test pad. The package further includes a substrate; and a plurality of microbumps configured to electrically connect the semiconductor chip to the substrate, wherein each microbump of the plurality of microbumps is electrically connected to a corresponding microbump pad of the plurality of microbump pads. The package further includes a package substrate, wherein the package substrate comprises a bump pad, wherein an area of the bump pad is greater than a combined area of the test pad and the plurality of microbump pads. The package further includes a bump configured to electrically connect the substrate to the package substrate.

公开(公告)号：US09305902B1

公开(公告)日：2016-04-05

申请号：US14964464

申请日：2015-12-09

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Po Chun Lin

IPC分类号： H01L21/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/0616 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1435 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00

摘要： A semiconductor device includes a plurality of conductors for connecting another semiconductor device. Each conductor connects to a chip select pad within the semiconductor device through an upper vertical connection formed through an insulation layer formed on a substrate or connected to a straight vertical connection formed through the substrate and the insulation layer. The semiconductor device further includes a plurality of lower vertical connections formed through the substrate and correspondingly connecting to the chip select pads and a chip select terminal. The chip select terminal electrically connects to the die circuit of the semiconductor device while the chip select pads are electrically isolated from the die circuit. The lower vertical connections and the straight vertical connection can be arranged in two dimensions.

公开(公告)号：US09240381B2

公开(公告)日：2016-01-19

申请号：US14034975

申请日：2013-09-24

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Po Chun Lin

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/0616 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1435 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00

摘要： A semiconductor device includes a plurality of conductors for connecting another semiconductor device. Each conductor connects to a chip select pad within the semiconductor device through an upper vertical connection formed through an insulation layer formed on a substrate or connected to a straight vertical connection formed through the substrate and the insulation layer. The semiconductor device further includes a plurality of lower vertical connections formed through the substrate and correspondingly connecting to the chip select pads and a chip select terminal. The chip select terminal electrically connects to the die circuit of the semiconductor device while the chip select pads are electrically isolated from the die circuit. The lower vertical connections and the straight vertical connection can be arranged in two dimensions.

摘要翻译： 半导体器件包括用于连接另一半导体器件的多个导体。 每个导体通过形成在衬底上形成的绝缘层或连接到通过衬底和绝缘层形成的直立垂直连接的上垂直连接而连接到半导体器件内的芯片选择焊盘。 半导体器件还包括通过衬底形成的多个下垂直连接，并且相应地连接到芯片选择焊盘和芯片选择端。 芯片选择端子电连接到半导体器件的管芯电路，而芯片选择焊盘与裸片电路电隔离。 下垂直连接和垂直垂直连接可以在两个方面布置。

公开(公告)号：US20140327464A1

公开(公告)日：2014-11-06

申请号：US14331791

申请日：2014-07-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Cheng WU ,  Hsien-Pin HU ,  Shang-Yun HOU ,  Shin-Puu JENG ,  Chen-Hua YU ,  Chao-Hsiang YANG

IPC分类号： G01R31/28

CPC分类号： G01R31/2896 ,  G01R1/0416 ,  G01R31/2601 ,  G01R31/2884 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02377 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/0614 ,  H01L2224/0616 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16238 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014

摘要： A test structure including an array of microbumps electrically connecting a chip and a substrate, wherein a width of each microbump of the array of microbumps is equal to or less than about 50 microns (μm). The test structure further includes an interconnect structure connected to the array of microbumps. The test structure further includes an array of test pads around a periphery of the array of microbumps, wherein a test pad of the array of test pads is connected to a corresponding microbump of the array of microbumps through the interconnect structure. A width of the test pad is greater than a width of the corresponding microbump, and the test pad is adapted to be covered after circuit probing by a passivation material to prevent particle and corrosion issues.

摘要翻译： 一种测试结构，其包括将芯片和基板电连接的微型阵列阵列，其中微胶片阵列的每个微型块的宽度等于或小于约50微米（μm）。 测试结构还包括连接到微丸阵列的互连结构。 该测试结构进一步包括围绕微胶片阵列周边的测试焊盘的阵列，其中测试焊盘阵列的测试焊盘通过互连结构连接到微胶片阵列的对应微型块。 测试垫的宽度大于对应的微型块的宽度，并且测试垫适于在通过钝化材料的电路探测之后被覆盖以防止颗粒和腐蚀问题。

公开(公告)号：US20130087910A1

公开(公告)日：2013-04-11

申请号：US13543907

申请日：2012-07-09

申请人： RAMLAH BINTE ABDUL RAZAK

发明人： RAMLAH BINTE ABDUL RAZAK

IPC分类号： H01L23/498

CPC分类号： H01L24/06 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/0603 ,  H01L2224/0616 ,  H01L2224/09104 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

摘要： A semiconductor die includes a first contact stack including a first UBM pad on a first die pad, a second contact stack including a second UBM pad on a second die pad, and a third contact stack including a third UBM pad on a third die pad. The second UBM pad perimeter is shorter than the first UBM pad perimeter, and the third UBM pad perimeter is longer than the second UBM pad perimeter. A first solder bump is on the first UBM pad, a second solder bump is on the second UBM pad, and a third solder bump is on the third UBM pad. The first solder bump, second solder bump and third solder bump all have different sizes.

摘要翻译： 半导体管芯包括第一接触堆叠，第一接触堆叠包括在第一管芯焊盘上的第一UBM焊盘，在第二管芯焊盘上包括第二UBM焊盘的第二接触堆叠，以及在第三管芯焊盘上包括第三UBM焊盘的第三接触堆叠。 第二UBM垫周长比第一UBM垫周长短，而第三UBM垫周长比第二UBM垫周长长。 第一个焊料凸点位于第一个UBM焊盘上，第二个焊料凸块位于第二个UBM焊盘上，第三个焊料凸块位于第三个UBM焊盘上。 第一焊料凸块，第二焊料凸块和第三焊料凸块都具有不同的尺寸。

公开(公告)号：US20130017669A1

公开(公告)日：2013-01-17

申请号：US13612348

申请日：2012-09-12

申请人： Shoetsu Kogawa ,  Satoru Nakayama ,  Seigo Kamata ,  Shigemitsu Seito

发明人： Shoetsu Kogawa ,  Satoru Nakayama ,  Seigo Kamata ,  Shigemitsu Seito

IPC分类号： H01L21/78

CPC分类号： H01L21/304 ,  H01L21/78 ,  H01L23/585 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02166 ,  H01L2224/05014 ,  H01L2224/05095 ,  H01L2224/05554 ,  H01L2224/0616 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/00

摘要： A method to prevent contamination of the principal surface side in a process of grinding the back surface side of a semiconductor wafer. At an intersection of a scribe region of a semiconductor wafer whose back surface side is to be ground, a plurality of insulating layers is laminated over the principal surface in the same manner as an insulating layer constituting a wiring layer laminated over a device region. Moreover, in the same layer as an uppermost wiring disposed at the uppermost layer among a plurality of the wiring layers formed for a device region, a metal pattern is formed. Furthermore, a second insulating layer covering the uppermost wiring is also formed over the metal pattern so as to cover the same.

摘要翻译： 在研磨半导体晶片的背面侧的工序中，防止主面侧的污染的方法。 在要被研磨的背面侧的半导体晶片的划片区域的交点处，以与构成层叠在器件区域上的布线层的绝缘层相同的方式，在主表面上层叠多个绝缘层。 此外，在与用于器件区域形成的多个布线层中的布置在最上层的最上布线相同的层中，形成金属图案。 此外，覆盖最上面布线的第二绝缘层也形成在金属图案上以覆盖其上。

公开(公告)号：US08298919B2

公开(公告)日：2012-10-30

申请号：US12978944

申请日：2010-12-27

申请人： Shoetsu Kogawa ,  Satoru Nakayama ,  Seigo Kamata ,  Shigemitsu Seito

发明人： Shoetsu Kogawa ,  Satoru Nakayama ,  Seigo Kamata ,  Shigemitsu Seito

IPC分类号： H01L23/544 ,  H01L21/78

CPC分类号： H01L21/304 ,  H01L21/78 ,  H01L23/585 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02166 ,  H01L2224/05014 ,  H01L2224/05095 ,  H01L2224/05554 ,  H01L2224/0616 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/00

摘要： A method to prevent contamination of the principal surface side in a process of grinding the back surface side of a semiconductor wafer. At an intersection of a scribe region of a semiconductor wafer whose back surface side is to be ground, a plurality of insulating layers is laminated over the principal surface in the same manner as an insulating layer constituting a wiring layer laminated over a device region. Moreover, in the same layer as an uppermost wiring disposed at the uppermost layer among a plurality of the wiring layers formed for a device region, a metal pattern is formed. Furthermore, a second insulating layer covering the uppermost wiring is also formed over the metal pattern so as to cover the same.

摘要翻译： 在研磨半导体晶片的背面侧的工序中，防止主面侧的污染的方法。 在要被研磨的背面侧的半导体晶片的划片区域的交点处，以与构成层叠在器件区域上的布线层的绝缘层相同的方式，在主表面上层叠多个绝缘层。 此外，在与用于器件区域形成的多个布线层中的布置在最上层的最上布线相同的层中，形成金属图案。 此外，覆盖最上面布线的第二绝缘层也形成在金属图案上以覆盖其上。

公开(公告)号：US20240355858A1

公开(公告)日：2024-10-24

申请号：US18136762

申请日：2023-04-19

申请人： OMNIVISION TECHNOLOGIES, INC.

发明人： Takayuki Goto ,  Kazufumi Watanabe ,  Rui Wang

IPC分类号： H01L27/146 ,  H01L23/00

CPC分类号： H01L27/14636 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L27/14634 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/0615 ,  H01L2224/0616 ,  H01L2224/06505 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/08501

摘要： A stacked semiconductor device comprising a first semiconductor substrate, a second semiconductor substrate, an insulating medium disposed between the first semiconductor substrate and the second semiconductor substrate, a plurality of connection pads including a first connection pad and a second connection pad, a first connection pad shield structure, and a second connection pad shield structure. The plurality of connection pads is disposed within the insulating medium and configured to provide one or more electrical connections extending between the first semiconductor substrate and the second semiconductor substrate. The first connection pad is disposed between the first connection pad shield structure and the second connection pad shield structure.

公开(公告)号：US20240355765A1

公开(公告)日：2024-10-24

申请号：US18136757

申请日：2023-04-19

申请人： OMNIVISION TECHNOLOGIES, INC.

发明人： Takayuki Goto ,  Kazufumi Watanabe ,  Rui Wang

IPC分类号： H01L23/00 ,  H01L27/146

CPC分类号： H01L24/06 ,  H01L24/05 ,  H01L24/08 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/0615 ,  H01L2224/0616 ,  H01L2224/06177 ,  H01L2224/06505 ,  H01L2224/06517 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/08501 ,  H01L2224/09505

摘要： A stacked semiconductor device comprising a first semiconductor substrate, a second semiconductor substrate, an insulating medium disposed between the first semiconductor substrate and the second semiconductor substrate, a plurality of connection pads including a first connection pad and a second connection pad adjacent to the first connection pad, and a first connection pad shield structure disposed within the insulating medium between at least the first connection pad and the second connection pad is described. The plurality of connection pads is disposed within the insulating medium and configured to provide one or more electrical connections extending between the first semiconductor substrate and the second semiconductor substrate.