公开(公告)号：US12107054B2

公开(公告)日：2024-10-01

申请号：US18173080

申请日：2023-02-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Nuo Xu ,  Yuan-Hao Chang ,  Po-Sheng Lu ,  Zhiqiang Wu

IPC分类号： H01L23/552 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L23/552 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/13005 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2924/1435

摘要： A semiconductor package, a semiconductor device and a shielding housing for a semiconductor package are provided. The semiconductor package includes a semiconductor chip having a first region and a second region beside the first region; and a shielding housing encasing the semiconductor chip, made of a magnetic permeable material, and including a first shielding plate, a second shielding plate opposite to the first shielding plate and a shielding wall extending between the first shielding plate and the second shielding plate. The first shielding plate has an opening exposing the first region and includes a raised portion surrounding the opening and a flat portion beside the raised portion and shielding the second region. A first distance from a level of the semiconductor chip to an outer surface of the raised portion is greater than a second distance from the level to an outer surface of the flat portion.

公开(公告)号：US20240258228A1

公开(公告)日：2024-08-01

申请号：US18541630

申请日：2023-12-15

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Juneyoung Park ,  Heonjong Shin ,  Jaeran Jang ,  Doohyun Lee

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L23/49838 ,  H01L23/49822 ,  H01L24/08 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/08137 ,  H01L2224/08146 ,  H01L2224/16137 ,  H01L2224/16227 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/1431 ,  H01L2924/1435 ,  H01L2924/19041

摘要： An integrated circuit device includes a first substrate having a first surface and a second surface opposite to the first surface, and including an active device therein, BEOL structure disposed on the first surface of the first substrate and configured to route signals, a second substrate disposed on the first surface of the first substrate with the first BEOL structure disposed therebetween, and including a passive device therein, a power distribution structure disposed on the second surface of the first substrate, a first bonding structure positioned on the first BEOL structure, and a second bonding structure disposed between the first bonding structure and the second substrate.

公开(公告)号：US20240234376A9

公开(公告)日：2024-07-11

申请号：US18483211

申请日：2023-10-09

申请人： Samsung Electronics Co., Ltd.

发明人： Hyun Soo CHUNG ,  Young Lyong KIM

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H10B80/00

CPC分类号： H01L25/0657 ,  H01L23/3107 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0655 ,  H10B80/00 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2924/1431 ,  H01L2924/1435

摘要： A semiconductor package may include a circuit board, an interposer structure on the circuit board, a mold layer, and a first semiconductor chip and a second semiconductor chip spaced apart from each other in a first direction on a center region of the interposer structure and electrically connected to the interposer structure. The interposer structure may include a plurality of trenches in an edge region of the interposer structure and extending through the interposer structure. The mold layer may be in the plurality of trenches and may wrap the first and second semiconductor chips. The mold layer may include a penetrating portion in the plurality of trenches and a stack portion on the interposer structure. A bottom surface of the penetrating portion of the mold layer may be on a same plane as a bottom surface of the interposer structure.

公开(公告)号：US20240203854A1

公开(公告)日：2024-06-20

申请号：US18228209

申请日：2023-07-31

申请人： Samsung Electronics Co., Ltd.

发明人： Hyeon Jeong HWANG ,  Geun Woo KIM

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC分类号： H01L23/49827 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32146 ,  H01L2224/32235 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1058 ,  H01L2924/1433 ,  H01L2924/1435

摘要： A semiconductor package an interposer disposed on a substrate, a recess recessed from an upper surface of the interposer, a connection structure disposed inside the recess, a first post disposed on the upper surface of the interposer and electrically connected to the interposer, a second post disposed on an upper surface of the connection structure and electrically connected to the connection structure, a first lower semiconductor chip disposed between the first and second posts and disposed on the upper surface of the interposer and the upper surface of the connection structure. The first lower semiconductor chip is electrically connected to the second post through the connection structure, and a first upper semiconductor chip is disposed on an upper surface of the first lower semiconductor chip. The first upper semiconductor chip is electrically connected to the first lower semiconductor chip through the second post and the connection structure.

公开(公告)号：US11756918B2

公开(公告)日：2023-09-12

申请号：US17184511

申请日：2021-02-24

申请人： KIOXIA CORPORATION

发明人： Tsutomu Sano ,  Kazuya Maruyama ,  Satoru Takaku ,  Nobuhito Suzuya

IPC分类号： H01L25/065 ,  H01L23/00

CPC分类号： H01L24/46 ,  H01L24/06 ,  H01L25/0657 ,  H01L2224/06515 ,  H01L2224/46 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2924/1435

摘要： A semiconductor device includes a first terminal, a second terminal, and a plurality of third terminals on a substrate. Memory chips are stacked on the substrate in an offset manner. Each memory chip has first pads, second pads, and third pads thereon. A first bonding wire is electrically connected to the first terminal and physically connected to a first pad of each memory chip. A second bonding wire is electrically connected to the second terminal and physically connected to a second pad of each memory chip. A third bonding wire electrically connects one third terminal to a third pad on each memory chip. A fourth bonding wire is connected to the first bonding wire at a first pad on a first memory chip of the stack and another first pad on the first memory chip. The fourth bonding wire straddles over the second bonding wire and the third bonding wire.

公开(公告)号：US09875971B2

公开(公告)日：2018-01-23

申请号：US15080541

申请日：2016-03-24

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Bharat Bhushan ,  Juan Boon Tan ,  Wanbing Yi

IPC分类号： H01L43/12 ,  H01L29/82 ,  H01L23/552 ,  H01L23/29 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L23/552 ,  H01L21/486 ,  H01L21/563 ,  H01L23/295 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/0613 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/0616 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29355 ,  H01L2224/2936 ,  H01L2224/29393 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92225 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/1434 ,  H01L2924/1435 ,  H01L2924/15311 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00014

摘要： Magnetic random access memory (MRAM) packages with magnetic shield protections and methods of forming thereof are presented. Package contact traces are formed on the first major surface of the package substrate and package balls are formed on the second major surface of the package substrate. A die having active and inactive surfaces is provided on the first major surface of the package substrate. The die includes a magnetic storage element, such as an array of magnetic tunnel junctions (MTJs), formed in the die, die microbumps formed on the active surface. The package includes a top magnetic shield layer formed on the inactive surface of the die. The package may also include a first bottom magnetic shield in the form of magnetic shield traces disposed below the package contact traces. The package may further include a second bottom magnetic shield in the form of magnetic permeable underfill dielectric material. The package may also include a third bottom magnetic shield sandwiched between two thin package substrate layers of the package substrate.

公开(公告)号：US20170323682A1

公开(公告)日：2017-11-09

申请号：US15660552

申请日：2017-07-26

申请人： Silicon Storage Technology, Inc.

发明人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Mark Reiten

IPC分类号： G11C16/08 ,  G11C7/10 ,  H01L25/18 ,  G11C16/04 ,  H01L25/065 ,  H01L23/00

CPC分类号： G11C16/08 ,  G11C7/1045 ,  G11C7/1057 ,  G11C16/04 ,  G11C2207/105 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1435 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/157

摘要： A three-dimensional flash memory system is disclosed. The system comprises a memory array comprising a plurality of stacked dies, where each die comprises memory cells. The system further comprises a plurality of pins, where the function of at least some of the pins can be configured using a mechanism that selects a function for those pins from a plurality of possible functions.

公开(公告)号：US20170287879A1

公开(公告)日：2017-10-05

申请号：US15630084

申请日：2017-06-22

申请人： SK hynix Inc.

发明人： Sang Yong LEE

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L25/0657 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/29007 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73103 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/8114 ,  H01L2224/81385 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83 ,  H01L2224/8385 ,  H01L2224/9211 ,  H01L2224/92242 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06562 ,  H01L2924/1435 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81

摘要： The stack package includes a substrate body layer having a top surface and a bottom surface, first circuit patterns disposed on the bottom surface of the substrate body layer, second circuit patterns disposed on the top surface of the substrate body layer, a first semiconductor chip including first bumps, and a second semiconductor chip including second bumps. The first bumps extend through the substrate body layer to be electrically coupled to the first circuit patterns, and the second bumps extend past sidewalls of the first semiconductor chip to be electrically coupled to the second circuit patterns. The second semiconductor chip is stacked on the first semiconductor chip.

公开(公告)号：US09728522B2

公开(公告)日：2017-08-08

申请号：US15425859

申请日：2017-02-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： An-Jhih Su ,  Hsien-Wei Chen

IPC分类号： H01L21/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/16265 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1435 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

摘要： Packages and methods of manufacture thereof are described. A package may include a first package and a die structure disposed over the first package. The first package may include: a first encapsulant; a first via structure within the first encapsulant; a first die within the first encapsulant, at least a portion of the first encapsulant being interposed between a sidewall of the first die and a sidewall of the first via structure; a second die within the first encapsulant, an active side of the second die facing an active side of the first die; and a first via chip within the first encapsulant, the first via chip comprising one or more through vias, wherein the first via chip is disposed at the active side of the first die, and between the second die and the first via structure.

公开(公告)号：US09633957B2

公开(公告)日：2017-04-25

申请号：US14555736

申请日：2014-11-28

申请人： Infineon Technologies AG

发明人： Jochen Hilsenbeck ,  Jens Peter Konrath ,  Thomas Frank ,  Roland Rupp

IPC分类号： H01L23/532 ,  H01L23/00 ,  H01L23/31 ,  H01L23/58 ,  H01L29/43

CPC分类号： H01L24/05 ,  H01L23/3121 ,  H01L23/585 ,  H01L24/03 ,  H01L24/06 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/417 ,  H01L29/4238 ,  H01L29/43 ,  H01L29/7392 ,  H01L29/7396 ,  H01L29/74 ,  H01L29/7802 ,  H01L29/8083 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05558 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/06181 ,  H01L2224/45124 ,  H01L2924/01014 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/0105 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/1203 ,  H01L2924/12031 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1435 ,  H01L2924/1436 ,  H01L2924/1461 ,  H01L2924/3512

摘要： According to various embodiments, a semiconductor device may include: a layer stack formed at a surface of the semiconductor device, the layer stack including: a metallization layer including a first metal or metal alloy; a protection layer covering the metallization layer, the protection layer including a second metal or metal alloy, wherein the second metal or metal alloy is less noble than the first metal or metal alloy.