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1.发明授权公开(公告)号：US12107054B2
公开(公告)日：2024-10-01
申请号：US18173080
申请日：2023-02-23
发明人： Nuo Xu , Yuan-Hao Chang , Po-Sheng Lu , Zhiqiang Wu
IPC分类号： H01L23/552 , H01L23/00 , H01L25/065
CPC分类号： H01L23/552 , H01L24/13 , H01L25/0657 , H01L2224/13005 , H01L2225/06541 , H01L2225/06565 , H01L2225/06586 , H01L2924/1435
摘要： A semiconductor package, a semiconductor device and a shielding housing for a semiconductor package are provided. The semiconductor package includes a semiconductor chip having a first region and a second region beside the first region; and a shielding housing encasing the semiconductor chip, made of a magnetic permeable material, and including a first shielding plate, a second shielding plate opposite to the first shielding plate and a shielding wall extending between the first shielding plate and the second shielding plate. The first shielding plate has an opening exposing the first region and includes a raised portion surrounding the opening and a flat portion beside the raised portion and shielding the second region. A first distance from a level of the semiconductor chip to an outer surface of the raised portion is greater than a second distance from the level to an outer surface of the flat portion.
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2.发明公开公开(公告)号：US20240313067A1
公开(公告)日：2024-09-19
申请号：US18669199
申请日：2024-05-20
发明人： Yen-Tien Tung , Szu-Wei Huang , Zhi-Ren Xiao , Yin-Chuan Chuang , Yung-Chien Huang , Kuan-Ting Liu , Tzer-Min Shen , Chung-Wei Wu , Zhiqiang Wu
IPC分类号： H01L29/40 , H01L21/3205 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/786
CPC分类号： H01L29/401 , H01L21/32053 , H01L29/42392 , H01L29/4966 , H01L29/517 , H01L29/78696
摘要： A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.
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3.发明授权公开(公告)号：US11929409B2
公开(公告)日：2024-03-12
申请号：US17966086
申请日：2022-10-14
发明人： Wei Ju Lee , Chun-Fu Cheng , Chung-Wei Wu , Zhiqiang Wu
IPC分类号： H01L29/417 , H01L21/285 , H01L21/8238 , H01L27/092 , H01L29/08 , H01L29/45
CPC分类号： H01L29/41791 , H01L21/28518 , H01L21/823814 , H01L21/823821 , H01L21/823871 , H01L27/0924 , H01L29/0847 , H01L29/45
摘要： Semiconductor device includes a substrate having multiple fins formed from a substrate, a first source/drain feature comprising a first epitaxial layer in contact with a first fin, a second epitaxial layer formed on the first epitaxial layer, and a third epitaxial layer formed on the second epitaxial layer, the third epitaxial layer comprising a center portion and an edge portion that is at a different height than the center portion; a fourth epitaxial layer formed on the third epitaxial layer, a second source/drain feature adjacent the first source/drain feature, comprising a first epitaxial layer in contact with a second fin, a second epitaxial layer formed on the first epitaxial layer of the second source/drain feature, a third epitaxial layer formed on the second epitaxial layer of the second source/drain feature, the third epitaxial layer comprising a center portion and an edge portion that is at a different height than the center portion of the third epitaxial layer of the second source/drain feature; and a fourth epitaxial layer formed on the third epitaxial layer of the second source/drain feature.
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公开(公告)号：US11849589B2
公开(公告)日：2023-12-19
申请号：US17808635
申请日：2022-06-24
发明人： Han-Jong Chia , Yu-Ming Lin , Zhiqiang Wu , Sai-Hooi Yeong
CPC分类号： H10B51/30 , H01L28/90 , H01L29/40111 , H01L29/42364 , H01L29/6684 , H01L29/78391 , H10B53/30
摘要： A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a substrate having a first surface, a first conductive region and a second conductive region at the first surface, wherein the first conductive region is apart from the second conductive region, a gate feature, wherein a top surface of the gate feature is above the first conductive region, a stack unit coupled to the first conductive region, wherein the stack unit includes a plurality of ferroelectric layers stacking with a plurality of metal layers, wherein each of the plurality of ferroelectric layers separates adjacent two metal layers.
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公开(公告)号：US11716857B2
公开(公告)日：2023-08-01
申请号：US17351121
申请日：2021-06-17
发明人： Yu-Chien Chiu , Meng-Han Lin , Chun-Fu Cheng , Han-Jong Chia , Chung-Wei Wu , Zhiqiang Wu
CPC分类号： H10B51/20 , H01L29/0649 , H10B51/10 , H10B51/30
摘要： A semiconductor memory device includes a stack of alternating insulating layers and first conductive layers disposed over a substrate; a plurality of memory cell strings penetrating the stack over the substrate, each memory cell string comprising a central portion extending through the stack, a semiconductor layer surrounding the central portion, and a ferroelectric layer surrounding the semiconductor layer, and the central portion comprising a channel isolation structure and a second conductive layer and a third conductive layer at two sides of the channel isolation structure; and a plurality of cell isolation structures penetrating the conductive layers and the insulating layers over the substrate and disposed between two memory cell strings, each cell isolation structure comprising a top portion and a bottom portion adjoined to the top portion and different from the top portion.
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公开(公告)号：US11705177B2
公开(公告)日：2023-07-18
申请号：US17470854
申请日：2021-09-09
发明人： Peng-Chun Liou , Zhiqiang Wu , Chung-Wei Wu , Yi-Ching Liu , Yih Wang
CPC分类号： G11C11/2257 , G11C11/2255 , G11C11/2297 , H10B51/20
摘要： A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures are configured to be applied with respective different voltages in accordance with the varying width of the first and second conductive structures.
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公开(公告)号：US20230123764A1
公开(公告)日：2023-04-20
申请号：US17591141
申请日：2022-02-02
发明人： Nuo Xu , Yuan Hao Chang , Po-Sheng Lu , Zhiqiang Wu
摘要： An MRAM cell block and a magnetic shielding structure for the MRAM cell block are incorporated into a metal interconnect of an integrated circuit (IC) device. The magnetic shielding structure may be provided by metallization layers and via layers having wires and vias that incorporate a magnetic shielding material. The magnetic shielding material may form the wires and vias, form a liner around the wires, or may be a layer of the wires. The wires and vias may also include a metal that is more conductive than the magnetic shielding material. The metal interconnect may include layers above or below the magnetic shielding structure that lack the magnetic shielding material and are more conductive. The MRAM cell block with the magnetic shielding structure is optionally provided as a standalone memory device or incorporated into a 3-D IC device that includes a second substrate having a conventional metal interconnect.
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8.发明授权公开(公告)号：US11527622B2
公开(公告)日：2022-12-13
申请号：US17144794
申请日：2021-01-08
发明人： Yen-Tien Tung , Szu-Wei Huang , Zhi-Ren Xiao , Yin-Chuan Chuang , Yung-Chien Huang , Kuan-Ting Liu , Tzer-Min Shen , Chung-Wei Wu , Zhiqiang Wu
IPC分类号： H01L29/40 , H01L29/51 , H01L29/423 , H01L29/786 , H01L21/3205 , H01L29/49
摘要： A method includes providing a structure having a substrate and a channel layer over the substrate; forming a high-k gate dielectric layer over the channel layer; forming a work function metal layer over the high-k gate dielectric layer; forming a silicide layer over the work function metal layer; annealing the structure such that a first portion of the work function metal layer that interfaces with the high-k gate dielectric layer is doped with silicon elements from the silicide layer; removing the silicide layer; and forming a bulk metal layer over the work function metal layer.
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公开(公告)号：US20220367612A1
公开(公告)日：2022-11-17
申请号：US17875221
申请日：2022-07-27
发明人： Chih-Ching Wang , Wen-Hsing Hsieh , Jon-Hsu Ho , Wen-Yuan Chen , Chia-Ying Su , Chung-Wei Wu , Zhiqiang Wu
IPC分类号： H01L29/06 , H01L29/10 , H01L29/16 , H01L29/423 , H01L29/08
摘要： Embodiments relate to a semiconductor device structure including a first channel layer having a first surface and a second surface, a second channel layer having a first surface and a second surface, and the first and second channel layers are formed of a first material. The structure also includes a first dopant suppression layer in contact with the second surface of the first channel layer, and a second dopant suppression layer parallel to the first dopant suppression layer. The second dopant suppression layer is in contact with the first surface of the second channel layer, and the first and second dopant suppression layers each comprises carbon or fluorine. The structure further includes a gate dielectric layer in contact with the first and second dopant suppression layers and the first surface of the first channel layer, and a gate electrode layer disposed on the gate dielectric layer.
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公开(公告)号：US20220277782A1
公开(公告)日：2022-09-01
申请号：US17748560
申请日：2022-05-19
发明人： Gaurav Gupta , Zhiqiang Wu
摘要： In some embodiments, the present application provides a memory device. The memory device includes a memory cell array comprising a plurality of magnetic tunnel junction (MTJ) memory cells arranged in columns and rows, a read bias circuit connected to the memory cell array and configured to provide a reading bias for a MTJ memory cell of the memory cell array, and a first non-linear resistance device connected in series and between the MTJ memory cell and the read bias circuit. The first non-linear resistance device is configured to provide a first resistance when conducting a first current and a second resistance greater than the first resistance when conducting a second current smaller than the first current.
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