公开(公告)号：US20240256848A1

公开(公告)日：2024-08-01

申请号：US18632180

申请日：2024-04-10

申请人： Samsung Electronics Co., Ltd.

发明人： Borna J. Obradovic ,  Titash Rakshit ,  Mark S. Rodder

IPC分类号： G06N3/065 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/808 ,  H10B41/30

CPC分类号： G06N3/065 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/8083 ,  H10B41/30

摘要： A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.

公开(公告)号：US11972985B2

公开(公告)日：2024-04-30

申请号：US17418104

申请日：2019-12-25

申请人： NATIONAL UNIVERSITY CORPORATION HOKKAIDO UNIVERSITY

发明人： Katsuhiro Tomioka

IPC分类号： H01L29/06 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/808 ,  B82Y10/00

CPC分类号： H01L21/823885 ,  H01L21/823412 ,  H01L29/0669 ,  H01L29/8083 ,  B82Y10/00

摘要： This complementary switch element includes: a first TFET having a first conductive channel; and a second TFET having a second conductive channel. Each of the first TFET and the second TFET includes: a group IV semiconductor substrate doped in a first conductive type; a nanowire which is formed of a group III-V compound semiconductor and is disposed on the group IV semiconductor substrate; a first electrode connected to the group IV semiconductor substrate; a second electrode connected to the nanowire; and a gate electrode. The nanowire includes a first area connected to the group IV semiconductor substrate and a second area doped in a second conductive type. In the first TFET, the second electrode is a source electrode, and the first electrode is a drain electrode. In the second TFET, the first electrode is a source electrode, and the second electrode is a drain electrode.

公开(公告)号：US20230369486A1

公开(公告)日：2023-11-16

申请号：US18355683

申请日：2023-07-20

申请人： Wolfspeed, Inc.

发明人： Woongsun Kim ,  Sei-Hyung Ryu ,  Daniel Jenner Lichtenwalner ,  Naeem Islam

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/808

CPC分类号： H01L29/7813 ,  H01L29/66734 ,  H01L29/66924 ,  H01L29/8083

摘要： A power semiconductor device includes a semiconductor layer structure comprising a drift region of a first conductivity type and a well region of a second conductivity type, a plurality of gate trenches including respective gate insulating layers and gate electrodes therein extending into the drift region, respective shielding patterns of the second conductivity type in respective portions of the drift region adjacent the gate trenches, and respective conduction enhancing regions of the first conductivity type in the respective portions of the drift region. The drift region comprises a first concentration of dopants of the first conductivity type, and the respective conduction enhancing regions comprise a second concentration of the dopants of the first conductivity type that is higher than the first concentration. Related devices and fabrication methods are also discussed.

公开(公告)号：US20230206053A1

公开(公告)日：2023-06-29

申请号：US18111471

申请日：2023-02-17

申请人： Samsung Electronics Co., Ltd.

发明人： Borna J. Obradovic ,  Titash Rakshit ,  Mark S. Rodder

IPC分类号： G06N3/065 ,  H01L29/808 ,  H01L29/66 ,  H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  H10B41/30

CPC分类号： G06N3/065 ,  H01L29/8083 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/42324 ,  H01L29/40114 ,  H10B41/30

摘要： A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.

公开(公告)号：US20180241397A1

公开(公告)日：2018-08-23

申请号：US15954202

申请日：2018-04-16

申请人： HYPERION SEMICONDUCTORS OY

发明人： Artto AUROLA

IPC分类号： H03K19/0185 ,  H01L27/092 ,  H01L29/36 ,  H01L29/06

CPC分类号： H03K19/018521 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/098 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/1033 ,  H01L29/36 ,  H01L29/78 ,  H01L29/808 ,  H01L29/8083 ,  H03K19/0013 ,  H03K19/00315 ,  H03K19/094 ,  H03K19/0952 ,  H03K19/20

摘要： Disclosed is a semiconductor logic element including a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries including the described logic element.

公开(公告)号：US20180240872A9

公开(公告)日：2018-08-23

申请号：US14702592

申请日：2015-05-01

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Hamza Yilmaz ,  Daniel Ng ,  Lingping Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L21/306

CPC分类号： H01L29/0696 ,  H01L21/30625 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/0821 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/66893 ,  H01L29/7371 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

公开(公告)号：US20180226513A1

公开(公告)日：2018-08-09

申请号：US15947010

申请日：2018-04-06

申请人： United Silicon Carbide, Inc.

发明人： Zhongda Li ,  Anup Bhalla

IPC分类号： H01L29/808 ,  H01L29/66 ,  H01L21/02 ,  H01L29/45 ,  H01L29/16 ,  H01L29/10 ,  H01L29/06 ,  H01L21/768 ,  H01L21/04

CPC分类号： H01L29/8083 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/045 ,  H01L21/046 ,  H01L21/0465 ,  H01L21/047 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/76897 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66909

摘要： A vertical JFET made by a process using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

公开(公告)号：US20180219072A1

公开(公告)日：2018-08-02

申请号：US15882040

申请日：2018-01-29

申请人： Hua Su Dian Li (Su Zhou) Co. Ltd.

发明人： Gangfeng Ye

IPC分类号： H01L29/20 ,  H01L29/66 ,  H01L29/78 ,  H01L29/808 ,  H01L29/10

CPC分类号： H01L29/2003 ,  H01L29/0847 ,  H01L29/1058 ,  H01L29/41766 ,  H01L29/66462 ,  H01L29/66666 ,  H01L29/66916 ,  H01L29/7788 ,  H01L29/7827 ,  H01L29/8083

摘要： A vertical JFET is provided. The JFET is mixed with lateral channel structure and p-GaN gate structure. The JFET has a N+ implant source region. In one embodiment, a JFET is provided with a drain metal deposited over a backside of an N substrate, an n-type drift layer epitaxial grown over a topside of the N substrate, a buried P-type block layer deposited over the n-type drift layer, an implanted N+ source region on side walls of the lateral channel layer, and an source metal attached to the top of the p-layer and attached to the implanted N+ source region at the side. In one embodiment, the JFET further comprises a gate layer, and wherein the gate layer is a dielectric gate structure that enables a fully enhanced channel. In another embodiment, the gate layer is a p-type GaN gate structure that enables a partially enhanced channel.

公开(公告)号：US20180212045A1

公开(公告)日：2018-07-26

申请号：US15681597

申请日：2017-08-21

申请人： Qorvo US, Inc.

发明人： Jinqiao Xie ,  Xing Gu ,  Edward A. Beam, III

IPC分类号： H01L29/66 ,  H01L21/02

CPC分类号： H01L29/66909 ,  H01L21/02389 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02647 ,  H01L27/14679 ,  H01L29/0649 ,  H01L29/1066 ,  H01L29/1095 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/66734 ,  H01L29/66893 ,  H01L29/66924 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/8086 ,  H01L2924/13062

摘要： A precursor cell for a transistor having a foundation structure, a mask structure, and a gallium nitride (GaN) PN structure is provided. The mask structure is provided over the foundation structure to expose a first area of a top surface of the foundation structure. The GaN PN structure resides over the first area and at least a portion of the mask structure and has a continuous crystalline structure with no internal regrowth interfaces. The GaN PN structure comprises a drift region over the first area, a control region laterally adjacent the drift region, and a PN junction formed between the drift region and the control region. Since the drift region and the control region form the PN junction having no internal regrowth interfaces, the GaN PN structure has a continuous crystalline structure with reduced regrowth related defects at the interface of the drift region and the control region.

公开(公告)号：US20180190651A1

公开(公告)日：2018-07-05

申请号：US15861113

申请日：2018-01-03

申请人： Infineon Technologies AG

发明人： Ralf Siemieniec ,  Mihai Draghici ,  Jens Peter Konrath

IPC分类号： H01L27/07 ,  H01L29/47 ,  H01L29/80 ,  H01L29/868 ,  H01L29/16 ,  H01L29/66 ,  H01L29/808 ,  H01L29/45 ,  H01L29/40

CPC分类号： H01L27/0727 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/401 ,  H01L29/45 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/806 ,  H01L29/8083 ,  H01L29/868 ,  H01L29/872

摘要： A semiconductor device includes a semiconductor body having a first silicon carbide region and a second silicon carbide region which forms a pn-junction with the first silicon carbide region, a first metallization on a front side of the semiconductor body, a contact region that forms an Ohmic contact with the second silicon carbide region, and a barrier-layer between the first metallization and the contact region and that is in Ohmic connection with the first metallization and the contact region. The barrier-layer forms a Schottky-junction with the first silicon carbide region, and includes molybdenum nitride or tantalum nitride. Additional semiconductor device embodiments and corresponding methods of manufacture are described.