公开(公告)号：US10686035B2

公开(公告)日：2020-06-16

申请号：US16155066

申请日：2018-10-09

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Hamza Yilmaz ,  Daniel Ng ,  Lingping Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/737 ,  H01L29/808 ,  H01L29/861 ,  H01L29/872 ,  H01L29/739 ,  H01L21/306 ,  H01L29/10 ,  H01L29/78

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

公开(公告)号：US10608092B2

公开(公告)日：2020-03-31

申请号：US15844520

申请日：2017-12-16

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Hamza Yilmaz ,  John Chen ,  Daniel Ng ,  Wenjun Li

IPC分类号： H01L21/306 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/40 ,  H01L29/49 ,  H01L29/10 ,  H01L27/02 ,  H01L29/06 ,  H01L29/872 ,  H01L29/861 ,  H01L21/3065

摘要： This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.

公开(公告)号：US09502554B2

公开(公告)日：2016-11-22

申请号：US15004805

申请日：2016-01-22

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Madhur Bobde ,  Hamza Yilmaz ,  Sik Lui ,  Daniel Ng

IPC分类号： H01L29/76 ,  H01L29/78 ,  H01L27/04 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L27/02 ,  H01L29/40 ,  H01L29/47 ,  H01L21/225 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45

CPC分类号： H01L29/7813 ,  H01L21/2257 ,  H01L27/0251 ,  H01L27/04 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7808 ,  H01L29/7811

摘要： Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 本公开的方面描述了具有自对准源触点的高密度沟槽基功率MOSFET和用于制造这种器件的方法。 源极触点与衬垫自对准。 MOSFET也可以在衬底的下部包括可消除的屏蔽。 可消除的屏蔽可以被配置成使得在高排水偏压期间，屏蔽件基本上消耗掉。 要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US20160322459A1

公开(公告)日：2016-11-03

申请号：US14702592

申请日：2015-05-01

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Hamza Yilmaz ,  Daniel Ng ,  Lingping Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

IPC分类号： H01L29/06 ,  H01L21/306 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10

CPC分类号： H01L29/0696 ,  H01L21/30625 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/0821 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/66893 ,  H01L29/7371 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件，半导体衬底具有多个沟槽。 每个沟槽填充有多个交替导电类型的外延层，其构成纳米管，其功能是作为沿着侧壁方向延伸的层堆叠的导电通道，“间隙填充”层填充基本上位于其上的纳米管之间的合并间隙 每个沟渠的中心。 “间隙填料”层可以非常轻掺杂硅或生长和沉积的介电层。 在一个示例性实施例中，多个沟槽被柱柱分隔开，柱柱各自具有沟槽宽度的大约一半到三分之一的宽度。

公开(公告)号：US20160172482A1

公开(公告)日：2016-06-16

申请号：US14565668

申请日：2014-12-10

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Madhur Bobde ,  Sik Lui ,  Hamza Yilmaz ,  Jongoh Kim ,  Daniel Ng

IPC分类号： H01L29/78 ,  H01L29/36 ,  H01L29/08 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423

CPC分类号： H01L29/66734 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66492 ,  H01L29/66666 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/872 ,  H01L29/8725

摘要： A plurality of gate trenches is formed into an epitaxial region of a first conductivity type over a semiconductor substrate. One or more contact trenches are formed into the epitaxial region, each between two adjacent gate trenches. One or more source regions of the first conductivity type are formed in a top portion of the epitaxial region between a contact trench and a gate trench. A barrier metal is formed inside each contact trench. Each gate trench is substantially filled with a conductive material separated from trench walls by a layer of dielectric material to form a gate. A heavily doped well region of a conductivity opposite the first type is provided in the epitaxial region proximate a bottom portion of each of the contact trenches. A horizontal width of a gap between the well region and the gate trench is about 0.05 μm to 0.2 μm.

摘要翻译： 多个栅极沟槽在半导体衬底上形成为第一导电类型的外延区域。 一个或多个接触沟槽形成到外延区域中，每个在两个相邻的栅极沟槽之间。 第一导电类型的一个或多个源极区域形成在接触沟槽和栅极沟槽之间的外延区域的顶部。 在每个接触沟槽内形成阻挡金属。 每个栅极沟槽基本上填充有通过介电材料层与沟槽壁分离以形成栅极的导电材料。 在靠近每个接触沟槽的底部的外延区域中提供了与第一类型相反的导电性的重掺杂阱区。 阱区和栅极沟槽之间的间隙的水平宽度为约0.05μm至0.2μm。

公开(公告)号：US20140264571A1

公开(公告)日：2014-09-18

申请号：US14294520

申请日：2014-06-03

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Sik Lui ,  Yi Su ,  Daniel Ng ,  Daniel Calafut ,  Anup Bhalla

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L23/647 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L2224/0603 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A trench formed in a body layer and epitaxial layer of a substrate is lined with a dielectric layer. A shield electrode formed within a lower portion of the trench is insulated by the dielectric layer. A gate electrode formed in the trench above the shield electrode is insulated from the shield electrode by another dielectric layer. One or more source regions formed within the body layer is adjacent a sidewall of the trench. A source pad formed above the body layer is electrically connected to the source regions and insulated from the gate electrode and shield electrode. The source pad provides an external contact to the source region. A gate pad provides an external contact to the gate electrode. A shield electrode pad provides an external contact to the shield electrode. A resistive element is electrically connected between the shield electrode pad and a source lead.

摘要翻译： 形成在体层中的沟槽和衬底的外延层衬有介电层。 形成在沟槽下部的屏蔽电极被电介质层绝缘。 形成在屏蔽电极上方的沟槽中的栅电极通过另一介质层与屏蔽电极绝缘。 形成在体层内的一个或多个源极区域与沟槽的侧壁相邻。 形成在主体层上方的源极焊盘电连接到源极区域并与栅电极和屏蔽电极绝缘。 源极焊盘提供与源极区域的外部接触。 栅极焊盘提供与栅电极的外部接触。 屏蔽电极焊盘提供与屏蔽电极的外部接触。 电阻元件电连接在屏蔽电极焊盘和源极之间。

公开(公告)号：US20140235024A1

公开(公告)日：2014-08-21

申请号：US14264318

申请日：2014-04-29

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Ji Pan ,  Daniel Ng ,  Sung-Shan Tai ,  Anup Bhalla

IPC分类号： H01L21/265 ,  H01L21/8234

CPC分类号： H01L21/26513 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/82 ,  H01L21/823412 ,  H01L27/0629 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/41766 ,  H01L29/47 ,  H01L29/4916 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872

摘要： Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)

摘要翻译： 公开了一种用于制造与肖特基二极管（MOSFET / SKY）集成的MOSFET的方法。 栅极沟槽形成在覆盖半导体衬底的外延层中，栅极材料沉积在其中。 主体，源极，电介质区域依次形成在外延层和栅极沟槽上。 通过定义源极接触深度（SCD）的电介质和源极区域，用垂直侧壁蚀刻顶部接触沟槽（TCT），所述垂直侧壁限定肖特基二极管横截面宽度SDCW; 并通过全身接触深度（TBCD）部分进入体区。 身体接触深度（BCD）

公开(公告)号：US09356132B2

公开(公告)日：2016-05-31

申请号：US14318408

申请日：2014-06-27

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Yi Su ,  Daniel Ng ,  Anup Bhalla ,  Hong Chang ,  Jongoh Kim ,  John Chen

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/872 ,  H01L29/40 ,  H01L29/08 ,  H01L21/265 ,  H01L29/417 ,  H01L29/423 ,  H01L29/47 ,  H01L29/49 ,  H01L29/06

CPC分类号： H01L29/7801 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0891 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/47 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/782 ,  H01L29/872

摘要： A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.

公开(公告)号：US20150214312A1

公开(公告)日：2015-07-30

申请号：US14684570

申请日：2015-04-13

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Xiaobin Wang ,  Anup Bhalla ,  Hamza Yilmaz ,  Daniel Ng

IPC分类号： H01L29/40 ,  H01L29/06

CPC分类号： H01L29/407 ,  H01L21/76205 ,  H01L29/04 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.

摘要翻译： 公开了具有多个嵌入式电位扩展电容结构（TSMEC）和方法的端接结构，用于在具有底部漏电极的体半导体层（BSL）的顶部端接邻近的沟槽MOSFET。 BSL具有支持漏极 - 源极电压（DSV）的近端体半导体壁（PBSW），并将TSMEC与沟槽MOSFET分离。 TSMEC具有由PBSW和远端体半导体壁（DBSW）界定的氧化物填充的大深沟槽（OFLDT）。 OFLDT包括位于大深度氧化物沟槽内部以及PBSW和DBSW之间的BSL中的大型深层氧化物沟槽和嵌入式电容结构（EBCS），用于在其间空间扩展DSV。 在一个实施例中，EBCS包含OFLDT的交错导电嵌入式多晶半导体区域（EPSR）和氧化物柱（OXC），与PBSW相邻的近端EPSR连接到活动上部源区域，并且与DBSW相邻的远端EPSR被连接到 星展集团

公开(公告)号：US20150137227A1

公开(公告)日：2015-05-21

申请号：US14566294

申请日：2014-12-10

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Madhur Bobde ,  Hamza Yilmaz ,  Sik Lui ,  Daniel Ng

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/47 ,  H01L29/40 ,  H01L27/02

CPC分类号： H01L29/7813 ,  H01L21/2257 ,  H01L27/0251 ,  H01L27/04 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7808 ,  H01L29/7811

摘要： Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 本公开的方面描述了具有自对准源触点的高密度沟槽基功率MOSFET和用于制造这种器件的方法。 源触点与间隔物自对准，并且有源器件可以具有两步栅极氧化物。 下部可以具有比栅极氧化物的上部的厚度大的厚度。 MOSFET也可以在衬底的下部包括可消除的屏蔽。 可消除的屏蔽可以被配置成使得在高排水偏压期间，屏蔽件基本上消耗掉。 要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。