公开(公告)号：US12009431B2

公开(公告)日：2024-06-11

申请号：US17929440

申请日：2022-09-02

Applicant: Epinovatech AB

Inventor： Martin Andreas Olsson

IPC: H01L29/78 ,  H01L21/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/775 ,  H01L33/06 ,  H01L33/24 ,  H01L33/32 ,  H10N60/10 ,  H10N60/83 ,  H10N60/85 ,  G01N27/414 ,  G06N10/00 ,  H01L29/417

CPC classification number: H01L29/7851 ,  H01L21/02381 ,  H01L21/02527 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L27/0924 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/1606 ,  H01L29/20 ,  H01L29/775 ,  H01L33/06 ,  H01L33/24 ,  H01L33/32 ,  H10N60/128 ,  H10N60/83 ,  H10N60/85 ,  G01N27/4146 ,  G06N10/00 ,  H01L29/41791

Abstract: A reinforced thin-film device is disclosed. The reinforced thin-film device comprising: a substrate having a top surface for supporting an epilayer; a mask layer patterned with a plurality of nanosize cavities disposed on said substrate to form a needle pad; a thin-film of, relative to the substrate, lattice-mismatched semiconductor disposed on said mask layer, wherein said thin-film comprises a plurality of in parallel spaced semiconductor needles of said lattice-mismatched semiconductor embedded in said thin-film, wherein said plurality of semiconductor needles are vertically disposed in the axial direction towards said substrate in said plurality of nanosize cavities of said mask layer; a, relative to the substrate, lattice-mismatched semiconductor epilayer provided on said thin-film and supported thereby; and a FinFET transistor arranged on the lattice-mismatched semiconductor epilayer. The FinFET transistor comprising: a fin semiconductor structure comprising an elongate protruding core portion, the fin semiconductor structure being arranged on the lattice-mismatched semiconductor epilayer, a first and a second nanostructured electrode radially enclosing respectively a source end and a drain end of the protruding core portion, and a nanostructured gate electrode radially enclosing a central portion of the protruding core portion, the central portion being a portion of the protruding core portion between the source end and the drain end.

公开(公告)号：US20240096709A1

公开(公告)日：2024-03-21

申请号：US18343634

申请日：2023-06-28

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/823807 ,  H01L29/0676 ,  H01L29/4238 ,  H01L29/66439 ,  H01L29/775

Abstract: Disclosed are a semiconductor device with a spacer and a C-shaped channel portion, a method of manufacturing the same, and an electronic apparatus including the semiconductor device. The semiconductor device may include: a channel portion on a substrate, wherein the channel portion includes a curved nanosheet or nanowire with a C-shaped cross-section; a first source/drain portion and a second source/drain portion respectively located at upper and lower ends of the channel portion with respect to the substrate; a first gate stack and a second gate stack located on opposite sides of the channel portion; a first spacer located between the first gate stack and the first source/drain portion and between the first gate stack and the second source/drain portion respectively; and a second spacer located between the second gate stack and the first source/drain portion and between the second gate stack and the second source/drain portion respectively.

公开(公告)号：US20240006500A1

公开(公告)日：2024-01-04

申请号：US17855411

申请日：2022-06-30

Applicant: International Business Machines Corporation

Inventor： Tsung-Sheng Kang ,  Ruqiang Bao ,  Curtis S. Durfee ,  Tao Li

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088 ,  H01L29/04 ,  H01L21/822 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L29/0676 ,  H01L29/78696 ,  H01L27/088 ,  H01L29/045 ,  H01L21/8221 ,  H01L21/823412

Abstract: An integrated circuit structure includes a first combsheet field effect transistor (FET), which includes: a semiconductor substrate; a first plurality of semiconductor nanosheets that extend along a crystallographic direction and that have horizontal surfaces oriented in (100) crystallographic planes and vertical sidewalls oriented in (110) crystallographic planes; and a semiconductor fin that is integrally attached to the nanosheets, extends along the nanosheets, and has horizontal sidewalls oriented in (100) crystallographic planes and vertical surfaces oriented in (110) crystallographic planes.

公开(公告)号：US11808722B2

公开(公告)日：2023-11-07

申请号：US17897408

申请日：2022-08-29

Applicant: NanoDX, Inc.

Inventor： Farhad Khosravi ,  David Bastable ,  Sergey A. Dryga

IPC: G01N27/04 ,  G01N33/487 ,  G01N27/403 ,  G01N27/414 ,  H01L29/06 ,  G01N27/327 ,  A61B5/1477

CPC classification number: G01N27/04 ,  A61B5/1477 ,  G01N27/327 ,  G01N27/3278 ,  G01N27/403 ,  G01N27/414 ,  G01N33/48707 ,  H01L29/0676

Abstract: Sensors having an advantageous design and methods for fabricating such sensors are generally provided. Some sensors described herein comprise pairs of electrodes having radial symmetry, pairs of nested electrodes, and/or nanowires. Some embodiments relate to fabricating electrodes by methods in which nanowires are deposited from a fluid contacted with a substrate in a manner such that it evaporates and is replenished.

公开(公告)号：US20230352575A1

公开(公告)日：2023-11-02

申请号：US17999605

申请日：2021-05-27

Applicant: Epinovatech AB

Inventor： Martin Andreas Olsson

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7788 ,  H01L29/0676 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/0646 ,  H01L29/2003

Abstract: There is provided a vertical high-electron-mobility transistor, HEMT (100), comprising: a drain contact (410), a nanowire layer (500) arranged on the drain contact (410) and comprising at least one vertical nanowire (510) and a supporting material (520) laterally enclosing the at least one vertical nanowire (510), a heterostructure (600) arranged on the nanowire layer and comprising an AIGaN-layer (610) and a GaN-layer (620) together forming a heterojunction, at least one source contact (420a, 420b) in contact with the heterostructure (600), and a gate contact (430) in contact with the heterostructure (600), arranged above the at least one vertical nanowire (510), wherein the at least one vertical nanowire (510) is forming an electron transport channel between the drain contact and the heterostructure. There is also provided a method for producing a vertical HEMT (100).

公开(公告)号：US11756961B2

公开(公告)日：2023-09-12

申请号：US17584801

申请日：2022-01-26

Applicant: International Business Machines Corporation

Inventor： Tsung-Sheng Kang ,  Tao Li ,  Ardasheir Rahman ,  Praveen Joseph ,  Indira Seshadri ,  Ekmini Anuja De Silva

IPC: H01L27/092 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/823807 ,  H01L21/823885 ,  H01L27/1207 ,  H01L29/0676 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method includes forming a first semiconducting channel comprising a plurality of vertical nanowires and a second semiconducting channel comprising a plurality of vertical nanowires. The first semiconducting channel and the second semiconducting channel are formed in a stacked configuration. The plurality of vertical nanowires of the first semiconducting channel are formed in alternating positions relative to the plurality of vertical nanowires of the second semiconducting channel.

公开(公告)号：US11721733B2

公开(公告)日：2023-08-08

申请号：US17366934

申请日：2021-07-02

Applicant: LONGITUDE FLASH MEMORY SOLUTIONS LTD.

Inventor： Igor Polishchuk ,  Sagy Charel Levy ,  Krishnaswamy Ramkumar

IPC: H01L21/28 ,  H01L29/423 ,  G11C16/04 ,  H01L29/792 ,  H01L29/51 ,  H01L29/66 ,  B82Y10/00 ,  H10B41/40 ,  H10B43/00 ,  H10B43/30 ,  H10B43/40 ,  H10B43/50 ,  H01L29/49 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L29/4234 ,  B82Y10/00 ,  G11C16/0466 ,  H01L21/0214 ,  H01L21/02532 ,  H01L21/02595 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  H10B41/40 ,  H10B43/00 ,  H10B43/30 ,  H10B43/40 ,  H10B43/50

Abstract: Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the memory transistor comprises an oxide-nitride-oxide (ONO) stack on a surface of a semiconductor substrate, and a high work function gate electrode formed over a surface of the ONO stack. Preferably, the gate electrode comprises a doped polysilicon layer, and the ONO stack comprises multi-layer charge storing layer including at least a substantially trap free bottom oxynitride layer and a charge trapping top oxynitride layer. More preferably, the device also includes a metal oxide semiconductor (MOS) logic transistor formed on the same substrate, the logic transistor including a gate oxide and a high work function gate electrode. In certain embodiments, the dopant is a P+ dopant and the memory transistor comprises N-type (NMOS) silicon-oxide-nitride-oxide-silicon (SONOS) transistor while the logic transistor a P-type (PMOS) transistor. Other embodiments are also disclosed.

公开(公告)号：US11688827B2

公开(公告)日：2023-06-27

申请号：US17106515

申请日：2020-11-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nakhyun Kim ,  Junhee Choi ,  Jinjoo Park ,  Joohun Han

IPC: H01L33/24 ,  H01L25/16 ,  H01L29/06 ,  H01L33/32 ,  H01L25/075 ,  H01L33/44

CPC classification number: H01L33/24 ,  H01L25/0753 ,  H01L25/167 ,  H01L29/0676 ,  H01L33/32 ,  H01L33/44

Abstract: A nanorod semiconductor layer having a flat upper surface, a micro-LED including the nanorod semiconductor layer, a pixel plate including the micro-LED, a display device including the pixel plate, and an electronic device including the pixel plate are provided. The nanorod semiconductor layer includes: a main body; and an upper end formed from the main body, wherein the upper end includes: a first inclined surface; a second inclined surface facing the first inclined surface; and a flat upper surface between the first inclined surface and the second inclined surface, and a width of the upper end becomes narrower in an upward direction, and when a length of the upper end protruded from the main body (a thickness of the upper end) is L1, an inclination angle between a surface extending parallel to a surface selected from the first and second inclined surfaces and the flat upper surface is β, and a width of the main body is D, a width D1 of the flat upper surface satisfies Equation 1.

D1=D−(2×L1×tan β)  

公开(公告)号：US20190115427A1

公开(公告)日：2019-04-18

申请号：US16155066

申请日：2018-10-09

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Hamza Yilmaz ,  Daniel Ng ,  Lingping Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

IPC: H01L29/06 ,  H01L29/739 ,  H01L29/08 ,  H01L29/872 ,  H01L29/861 ,  H01L29/808 ,  H01L29/737 ,  H01L29/10 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L29/0676 ,  H01L21/30625 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0821 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/66893 ,  H01L29/7371 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

公开(公告)号：US20190043947A1

公开(公告)日：2019-02-07

申请号：US16046516

申请日：2018-07-26

Applicant: Alpha and Omega Semiconductor Incorporated

Inventor： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

IPC: H01L29/08 ,  H01L29/872 ,  H01L21/265 ,  H01L29/861 ,  H01L29/78 ,  H01L29/739 ,  H01L29/66 ,  H01L27/06 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/40 ,  H01L29/36 ,  H01L29/10

CPC classification number: H01L29/0886 ,  H01L21/26586 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0664 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0676 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/365 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/861 ,  H01L29/8613 ,  H01L29/872 ,  H01L29/8725

Abstract: Semiconductor devices are formed using a pair of thin epitaxial layers (nanotubes) of opposite conductivity type formed on sidewalls of dielectric-filled trenches. In one embodiment, a termination structure is formed in the termination area and includes a first termination cell formed in the termination area at an interface to the active area, the termination cell being formed in a mesa of the first semiconductor layer and having a first width; and an end termination cell being formed next to the first termination cell in the termination area, the end termination cell being formed in an end mesa of the first semiconductor layer and having a second width greater than the first width.