Superconductive Memory Cells and Devices
    1.
    发明公开

    公开(公告)号:US20240249770A1

    公开(公告)日:2024-07-25

    申请号:US18587872

    申请日:2024-02-26

    申请人: PsiQuantum Corp,

    发明人: Faraz Najafi

    摘要: An example memory cell includes a superconducting loop configured to receive a write current and form a persistent current that stores a data bit in the superconducting loop. The example memory cell further includes a superconducting wire coupled to the superconducting loop and configured to selectively read-out the data bit in the superconducting loop in response to a control signal. An example method of reading data from the memory cell includes receiving, at the superconducting loop, a write current to store a data bit in a superconducting loop, and forming a persistent current that circulates in the superconducting loop as a stored data bit. The example method further includes, in accordance with a control signal, transferring, via a superconducting wire of the memory cell that is coupled to the superconducting loop, at least a portion of the persistent current to an output of the memory cell.

    Methods and systems for atomic layer etching and atomic layer deposition

    公开(公告)号:US11864472B2

    公开(公告)日:2024-01-02

    申请号:US17373619

    申请日:2021-07-12

    IPC分类号: H10N60/01 H10N60/83

    CPC分类号: H10N60/01 H10N60/83

    摘要: A method for etching a surface including obtaining a structure comprising a plurality of nanowires on or above a substrate and a dielectric layer on or above the nanowires, wherein the dielectric layer comprises protrusions formed by the underlying nanowires; reacting a surface of the dielectric layer with a reactant, comprising a gas or a plasma, to form a reactive layer on the dielectric layer, wherein the reactive layer comprises a chemical compound including the reactant and elements of the dielectric layer and the reactive layer comprises sidewalls defined by the protrusions; and selectively etching the reactive layer, wherein the etching etches the protrusions laterally through the sidewalls so as to planarize the surface and remove or shrink the protrusions.

    Method for processing a semiconductor device with two closely spaced gates

    公开(公告)号:US11638391B2

    公开(公告)日:2023-04-25

    申请号:US17345827

    申请日:2021-06-11

    申请人: IMEC VZW

    摘要: A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.