Fabricating a device using a multilayer stack

    公开(公告)号:US11935748B2

    公开(公告)日:2024-03-19

    申请号:US16640411

    申请日:2017-12-07

    Applicant: Google LLC

    CPC classification number: H01L21/0274 G03F7/094 H01L21/32139

    Abstract: A method of fabricating a device is presented. The method includes forming a multilayer stack (101′, 102′, 103′) on a substrate (10′, 100′) which has a principal surface. The multilayer stack includes a supporting layer (102′) formed over the principal surface of the substrate and a photoresist layer (103′) formed on the supporting layer, patterning the multilayer stack to form at least one opening such that the photoresist layer is undercut by the supporting layer and anisotropically dry etching the substrate.

    REDUCING PARASITIC CAPACITANCE AND COUPLING TO INDUCTIVE COUPLER MODES

    公开(公告)号:US20210384401A1

    公开(公告)日:2021-12-09

    申请号:US17405373

    申请日:2021-08-18

    Applicant: Google LLC

    Abstract: A qubit coupling device includes: a dielectric substrate including a trench; a first superconductor layer on a surface of the dielectric substrate where an edge of the first superconductor layer extends along a first direction and at least a portion of the superconductor layer is in contact with the surface of the dielectric substrate, and where the superconductor layer is formed from a superconductor material exhibiting superconductor properties at or below a corresponding critical temperature; a length of the trench within the dielectric substrate is adjacent to and extends along an edge of the first superconductor layer in the first direction, and where the electric permittivity of the trench is less than the electric permittivity of the dielectric substrate.

    TWO-QUBIT GATES IMPLEMENTED WITH A TUNABLE COUPLER

    公开(公告)号:US20210182728A1

    公开(公告)日:2021-06-17

    申请号:US17271323

    申请日:2019-08-27

    Applicant: Google LLC

    Abstract: Methods, systems and apparatus for implementing two-qubit gates using a tunable coupler. In one aspect, a method of implementing a two-qubit gate includes: applying a unitary transformation control signal to a tunable coupler arranged between a first data qubit and a second data qubit to obtain a target unitary transformation of the first data qubit and the second data qubit, w'herein the unitary transformation control signal is applied to the tunable coupler over a predetermined period of time to allow coupling between the first data qubit and the second data qubit through the tunable coupler.

    Capping layer for reducing ion mill damage

    公开(公告)号:US10957841B2

    公开(公告)日:2021-03-23

    申请号:US16333505

    申请日:2016-09-15

    Applicant: Google LLC

    Abstract: A method of fabricating an electrical contact junction that allows current to flow includes: providing a substrate including a first layer of superconductor material; removing a native oxide of the superconductor material of the first layer from a first region of the first layer; forming a capping layer in contact with the first region of the first layer, in which the capping layer prevents reformation of the native oxide of the superconductor material in the first region; forming, after forming the capping layer, a second layer of superconductor material that electrically connects to the first region of the first layer of superconductor material to provide the electrical contact junction that allows current to flow.

    QUANTUM INFORMATION PROCESSING DEVICE FORMATION

    公开(公告)号:US20200381609A1

    公开(公告)日:2020-12-03

    申请号:US16640399

    申请日:2017-12-07

    Applicant: Google LLC

    Abstract: A method for forming at least part of a quantum information processing device is presented. The method includes providing a first electrically-conductive layer formed of a first electrically-conductive material (100′) on a principal surface of a substrate (10), depositing a layer of dielectric material on the first electrically-conductive material, patterning the layer of dielectric material to form a pad of dielectric material and to reveal a first region of the first electrically-conductive layer, depositing a second electrically-conductive layer (104′) on the pad of dielectric material and on the first region of the first electrically-conductive layer, patterning the second electrically-conductive layer and removing the pad of dielectric material using isotropic gas phase etching.

    REDUCING PARASITIC CAPACITANCE AND COUPLING TO INDUCTIVE COUPLER MODES

    公开(公告)号:US20190341540A1

    公开(公告)日:2019-11-07

    申请号:US16473779

    申请日:2017-12-15

    Applicant: Google LLC

    Abstract: A qubit coupling device includes: a dielectric substrate including a trench; a first superconductor layer on a surface of the dielectric substrate where an edge of the first superconductor layer extends along a first direction and at least a portion of the superconductor layer is in contact with the surface of the dielectric substrate, and where the superconductor layer is formed from a superconductor material exhibiting superconductor properties at or below a corresponding critical temperature; a length of the trench within the dielectric substrate is adjacent to and extends along an edge of the first superconductor layer in the first direction, and where the electric permittivity of the trench is less than the electric permittivity of the dielectric substrate.

    Fabrication of interlayer dielectrics with high quality interfaces for quantum computing devices

    公开(公告)号:US10403808B2

    公开(公告)日:2019-09-03

    申请号:US16066640

    申请日:2015-12-30

    Applicant: Google LLC

    Abstract: A method includes: providing a first wafer including a first substrate, a first insulator layer on the first substrate, and a first dielectric layer on the first insulator layer; providing a second wafer including a second substrate, a second insulator layer on the second substrate, and a second dielectric layer on the second insulator layer; forming a first superconductor layer on the first dielectric layer; forming a second superconductor layer on the second dielectric layer; joining a surface of the first superconductor layer to a surface of the second superconductor layer to form a wafer stack; and forming a third superconductor layer on exposed first surface of the first dielectric layer.

    FABRICATION OF INTERLAYER DIELECTRICS WITH HIGH QUALITY INTERFACES FOR QUANTUM COMPUTING DEVICES

    公开(公告)号:US20190027672A1

    公开(公告)日:2019-01-24

    申请号:US16066640

    申请日:2015-12-30

    Applicant: Google LLC

    CPC classification number: H01L39/24 G06N10/00 H01L39/02

    Abstract: A method includes: providing a first wafer including a first substrate, a first insulator layer on the first substrate, and a first dielectric layer on the first insulator layer; providing a second wafer including a second substrate, a second insulator layer on the second substrate, and a second dielectric layer on the second insulator layer; forming a first superconductor layer on the first dielectric layer; forming a second superconductor layer on the second dielectric layer; joining a surface of the first superconductor layer to a surface of the second superconductor layer to form a wafer stack; and forming a third superconductor layer on exposed first surface of the first dielectric layer.

    Fabricating a device using a multilayer stack

    公开(公告)号:US12288687B2

    公开(公告)日:2025-04-29

    申请号:US18438142

    申请日:2024-02-09

    Applicant: Google LLC

    Abstract: A method of fabricating a device is presented. The method includes forming a multilayer stack on a substrate which has a principal surface. The multilayer stack includes a supporting layer formed over the principal surface of the substrate and a photoresist layer formed on the supporting layer, patterning the multilayer stack to form at least one opening such that the photoresist layer is undercut by the supporting layer and anisotropically dry etching the substrate.

    Two-qubit gates implemented with a tunable coupler

    公开(公告)号:US12260297B2

    公开(公告)日:2025-03-25

    申请号:US17271323

    申请日:2019-08-27

    Applicant: Google LLC

    Abstract: Methods, systems and apparatus for implementing two-qubit gates using a tunable coupler. In one aspect, a method of implementing a two-qubit gate includes: applying a unitary transformation control signal to a tunable coupler arranged between a first data qubit and a second data qubit to obtain a target unitary transformation of the first data qubit and the second data qubit, wherein the unitary transformation control signal is applied to the tunable coupler over a predetermined period of time to allow coupling between the first data qubit and the second data qubit through the tunable coupler.

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