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公开(公告)号：US12082512B2
公开(公告)日：2024-09-03
申请号：US16662586
申请日：2019-10-24
Applicant: Microsoft Technology Licensing, LLC
Inventor： Georg Wolfgang Winkler , Roman Mykolayovych Lutchyn , Leonardus Petrus Kouwenhoven , Farhad Karimi
Abstract: A semiconductor-superconductor hybrid device comprises a semiconductor layer and a superconductor layer. The superconductor layer is arranged over an edge of the semiconductor layer so as to enable energy level hybridisation between the semiconductor layer and the superconductor layer. The semiconductor layer is arranged in a sandwich structure between first and second insulating layers, each insulating layer being in contact with a respective opposed face of the semiconductor layer. This configuration may allow for good control over the geometry of the semiconductor layer and may improve tolerance to manufacturing variations. The device may be useful in a quantum computer. Also provided is a method of manufacturing the device, and a method of inducing topological behaviour in the device.
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公开(公告)号：US20240284807A1
公开(公告)日：2024-08-22
申请号：US18573683
申请日：2022-05-23
Applicant: QDEVIL APS
Inventor： Soren ANDRESEN , Peter Ulrik KANN , Merlin VON SOOSTEN
Abstract: A sample holder for a quantum device, the sample holder comprising a first portion comprising a first cavity, a second portion comprising a second cavity, first fixing elements comprising a printed circuit board comprising one or more electrical conductor(s) and/or wave guide(s), and second fixing elements configured to fix the first and second portions to each other, wherein the quantum device is provided over and covering at least part of the first cavity, the quantum device is provided over and covering at least part of the second cavity, the quantum device is fixed to the first portion by the first fixing elements and the electrical conductor(s) and/or wave guide(s) is/are connected to the quantum device and extend to outside of the first and second portions.
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公开(公告)号：US20240284806A1
公开(公告)日：2024-08-22
申请号：US18568635
申请日：2021-06-29
Applicant: Microsoft Technology Licensing, LLC
Inventor： Gijsbertus de Lange , Pavel Aseev , Sebastian Heedt
CPC classification number: H10N60/128 , H10N60/01 , H10N60/83
Abstract: Described is a semiconductor device comprising a substrate having a surface; a mesa arranged on the surface of the substrate, the mesa having a perimeter; and one or more gate electrodes. The mesa is obtainable by selective area growth, and comprises a semiconductor heterostructure for hosting a 2-dimensional electron gas or a 2-dimensional hole gas. The one or more gate electrodes are configured to deplete electrically portions of the semiconductor heterostructure to define a boundary of an active region of the semiconductor heterostructure, the boundary being spaced from the perimeter of the mesa. By using a selective-area-grown mesa and defining the boundary of the active region electrostatically, improved electronic properties may be obtained, for example by avoiding the diffuse scattering of charge carriers. Also provided is a method for fabricating the device, and a use of one or more gate electrodes to define an active region of a semiconductor component.
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公开(公告)号：US20240224816A1
公开(公告)日：2024-07-04
申请号：US18554168
申请日：2021-04-29
Applicant: Microsoft Technology Licensing, LLC
Inventor： Pavel ASEEV
Abstract: A semiconductor device comprises a crystalline substrate and a nanowire arranged epitaxially on the crystalline substrate. The nanowire comprises: a gating layer arranged over the substrate, a quantum well arranged over the gating layer, an intermediate barrier arranged between the gating layer and the quantum well, and an upper barrier arranged over the quantum well. By incorporating a gating layer into the nanowire, bottom gating of the quantum well is made possible without requiring the substrate to incorporate the bottom gate. Also provided are a method of operating the semiconductor device, and a method of fabricating the semiconductor device.
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公开(公告)号：US12029142B2
公开(公告)日：2024-07-02
申请号：US17577808
申请日：2022-01-18
Applicant: Infineon Technologies Austria AG
Inventor： Wolfram Langheinrich , Claus Dahl
CPC classification number: H10N69/00 , H10N60/01 , H10N60/11 , H10N60/128 , G06N10/40
Abstract: A method of producing a quantum conveyor includes: forming a pair of screening gate electrodes in or on a semiconductor substrate and that extend between a first stationary quantum dot and a second stationary quantum dot, the pair of screening gate electrodes configured to delimit a channel of moveable quantum dots between the first stationary quantum dot and the second stationary quantum dot; forming, via a lithography process, a plurality of first planar transfer electrodes above the semiconductor substrate and that extend transverse to the channel of moveable quantum dots; and forming, via a self-aligned damascene process, a plurality of second planar transfer electrodes laterally interleaved with the first planar transfer electrodes, wherein the first planar transfer electrodes and the second planar transfer electrodes are configured to transfer quantum information between the first stationary quantum dot and the second stationary quantum dot through the channel of moveable quantum dots.
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Patent Agency Ranking
公开(公告)号：US11978571B2
公开(公告)日：2024-05-07
申请号：US16948241
申请日：2020-09-09
Applicant: Christopher M. Rey
Inventor： Christopher M. Rey
CPC classification number: H01B12/06 , H01B12/00 , H01F41/048 , H10N60/01 , H01B7/36 , Y10T29/49014 , Y10T29/49071
Abstract: A method of coiling a superconducting cable, where the superconducting cable is comprised of a plurality of stacked superconducting tapes, where the superconducting cable has a clocking feature that identifies an orientation of the superconducting tapes, the method comprising the step of orienting coils of the superconducting cable, such that a magnetic field from surrounding coils impinge upon a given coil at a desired angle, based upon an orientation of the clocking feature.
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公开(公告)号：US11778927B2
公开(公告)日：2023-10-03
申请号：US18008896
申请日：2021-08-05
Applicant: Quantum Motion Technologies Limited
Inventor： Sofia Patomaki , John Morton
CPC classification number: H10N60/128 , H03K17/92 , H10N60/01 , H10N60/11
Abstract: A silicon-based quantum device is provided. The device comprises: a first metallic structure (501); a second metallic structure (502) laterally separated from the first metallic structure; and an L-shaped elongate channel (520) defined by the separation between the first and second metallic structures; wherein the elongate channel has a vertex (505) connecting two elongate parts of the elongate channel. The device further comprises: a third metallic structure (518), mediator gate, positioned in the elongate channel; a fourth metallic structure (531) forming a first barrier gate, arranged at a first end of the third metallic structure; and a fifth metallic structure (532) forming a second barrier gate arranged at a second end of the third metallic structure. The first, second, third, fourth and fifth metallic structures are configured for connection to first, second, third, fourth and fifth electric potentials respectively. The first, second, fourth and fifth electric potentials are controllable to define an electrical potential well to confine quantum charge carriers in an elongate quantum dot beneath the elongate channel. The fourth and fifth electric potentials and the position of the fourth and fifth metallic structures define first and second ends of the elongate channel respectively. The width of the electrical potential well is defined by the position of the first and second metallic structures and their corresponding electric potentials; and the length of the electrical potential well is defined by the position of the fourth and fifth metallic structures and their corresponding electric potentials. The third electric potential is controllable to adjust quantum charge carrier energy levels in the electrical potential well.
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公开(公告)号：US20230284539A1
公开(公告)日：2023-09-07
申请号：US18179085
申请日：2023-03-06
Applicant: Terra Quantum AG
Inventor： Valerii Vinokour , Yakov Kopelevich
CPC classification number: H10N60/82 , H10N60/85 , H10N60/01 , H04L63/0428
Abstract: A superconductor device comprises a graphite structure, a first electrode, a second electrode, and a wrinkle region. The graphite structure comprises at least one topmost atomic layer. The first electrode is arranged over the at least one topmost atomic layer. The second electrode is arranged over the at least one topmost atomic layer and spaced apart from the first electrode. The wrinkle region is comprised in the at least one topmost atomic layer. The wrinkle region is arranged between the first electrode and the second electrode and comprises a plurality of wrinkles with a pair of wrinkles. The first electrode and the second electrode both electrically contact both wrinkles of the pair. A distance between the wrinkles of the pair is at most 0.2 μm.
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公开(公告)号：US11751490B2
公开(公告)日：2023-09-05
申请号：US17405373
申请日：2021-08-18
Applicant: Google LLC
Inventor： Anthony Edward Megrant
IPC: H10N60/83 , G06N10/00 , H10N60/01 , H10N69/00 , H01L21/768 , H10N60/10 , H10N60/85 , H01L21/285
CPC classification number: H10N60/83 , G06N10/00 , H10N60/01 , H10N69/00 , H01L21/2855 , H01L21/76891 , H10N60/0156 , H10N60/0912 , H10N60/10 , H10N60/855
Abstract: A qubit coupling device includes: a dielectric substrate including a trench; a first superconductor layer on a surface of the dielectric substrate where an edge of the first superconductor layer extends along a first direction and at least a portion of the superconductor layer is in contact with the surface of the dielectric substrate, and where the superconductor layer is formed from a superconductor material exhibiting superconductor properties at or below a corresponding critical temperature; a length of the trench within the dielectric substrate is adjacent to and extends along an edge of the first superconductor layer in the first direction, and where the electric permittivity of the trench is less than the electric permittivity of the dielectric substrate.
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公开(公告)号：US11696515B2
公开(公告)日：2023-07-04
申请号：US16640399
申请日：2017-12-07
Applicant: Google LLC
Inventor： Anthony Edward Megrant
CPC classification number: H10N60/0912 , G06N10/00 , H10N60/01
Abstract: A method for forming at least part of a quantum information processing device is presented. The method includes providing a first electrically-conductive layer formed of a first electrically-conductive material (100′) on a principal surface of a substrate (10), depositing a layer of dielectric material on the first electrically-conductive material, patterning the layer of dielectric material to form a pad of dielectric material and to reveal a first region of the first electrically-conductive layer, depositing a second electrically-conductive layer (104′) on the pad of dielectric material and on the first region of the first electrically-conductive layer, patterning the second electrically-conductive layer and removing the pad of dielectric material using isotropic gas phase etching.
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