公开(公告)号：US20240355892A1

公开(公告)日：2024-10-24

申请号：US18763081

申请日：2024-07-03

Applicant: ROHM CO., LTD.

Inventor： Yasunobu HAYASHI

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/40 ,  H01L29/51

CPC classification number: H01L29/4234 ,  H01L29/408 ,  H01L29/51 ,  H01L29/40117

Abstract: A semiconductor device includes a planar gate structure including a gate insulating film and a gate electrode, and a sidewall structure disposed adjacent to a lateral side of the planar gate structure. The sidewall structure includes a first insulating film and a second insulating film, and a charge storage film disposed between the first insulating film and the second insulating film. The first insulating film is adjacent to the planar gate structure. A ratio between a gate length L of the planar gate structure and a width WS of the sidewall structure is less than or equal to 300/75. Thereby, a semiconductor device having an improved data read and write reliability in a memory structure can be provided.

公开(公告)号：US12127385B2

公开(公告)日：2024-10-22

申请号：US17565738

申请日：2021-12-30

Applicant: Unisantis Electronics Singapore Pte. Ltd.

Inventor： Fujio Masuoka ,  Nozomu Harada

IPC: H01L21/768 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00 ,  H01L21/311

CPC classification number: H10B10/12 ,  H01L21/76816 ,  H01L29/4234 ,  H01L29/66666 ,  H01L29/7827 ,  H01L21/31116 ,  H01L21/31144

Abstract: In formation of an SRAM cell, a band-shaped contact hole C3 is formed that does not overlap, in plan view. N+ layers 32a, 32c, 32d, and 32f formed on and at outer peripheries of the top portions of Si pillars 6a, 6c, 6d, and 6f, that partly overlaps W layers 33b and 33e on P+ layers 32b and 32e connected to the top portions of Si pillars 6b and 6e, that is connected in both the X direction and the Y direction, and that extends in the Y direction. A power supply wiring metal layer Vdd that connects the P+ layers 32b and 32e through the contact hole C3 is formed. After formation of the power supply wiring metal layer Vdd, a word wiring metal layer WL is formed so as to be orthogonal to the power supply wiring metal layer Vdd in plan view.

公开(公告)号：US12096635B2

公开(公告)日：2024-09-17

申请号：US17722403

申请日：2022-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Ting Chen ,  Hsueh-Chun Hsiao

IPC: H10B43/30 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H10B43/30 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: An SONOS memory cell includes a silicon substrate. A tunnel silicon oxide layer, a silicon nitride layer and a silicon oxide layer are disposed from bottom to top on the silicon substrate. The silicon oxide layer includes two first silicon oxide layers and a second silicon oxide layer. A thickness of the silicon oxide layer is smaller than a thickness of each of the first silicon oxide layers. A control gate covers and contacts the silicon oxide layer. A first source/drain doping region and a second source/drain doping region are respectively disposed at two sides of the control gate. The silicon oxide layer has a cross section. The second silicon oxide layer is sandwiched between the two first silicon oxide layers on the cross section.

公开(公告)号：US12048157B2

公开(公告)日：2024-07-23

申请号：US17475660

申请日：2021-09-15

Applicant: Kioxia Corporation

Inventor： Shunsuke Okada ,  Tatsunori Isogai ,  Masaki Noguchi

IPC: H10B43/27 ,  H01L21/28 ,  H01L29/423 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H10B41/27

Abstract: A semiconductor storage device of an embodiment includes: a laminated body including electrode layers and insulating layers alternately stacked in a first direction; a semiconductor layer disposed in the laminated body; a first insulating film disposed between the laminated body and the semiconductor layer; a charge storage film disposed between the laminated body and the first insulating film, thicknesses of the charge storage film in a second direction crossing the first direction in the regions corresponding to the electrode layers being different from that in the regions corresponding to the insulating layers, the charge storage film comprising: a second insulating film disposed between the laminated body and the first insulating film, and a third insulating film disposed between the second insulating film and the regions corresponding to the electrode layers, the third insulating film having a density different from that of the second insulating film.

公开(公告)号：US12048156B2

公开(公告)日：2024-07-23

申请号：US17450726

申请日：2021-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shin-Hwan Kang ,  Sun-Il Shim ,  Seung Hyun

IPC: H10B43/27 ,  H01L23/535 ,  H01L29/423 ,  H01L29/45 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/535 ,  H01L29/4234 ,  H01L29/456 ,  H10B43/40

Abstract: A vertical memory device includes first gate electrodes stacked on a cell region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel extending through the first gate electrodes and extending in the vertical direction, a first contact plug structure contacting a corresponding one of the first gate electrodes, extending in the vertical direction, and including a first metal pattern, a first barrier pattern covering a lower surface and a sidewall of the first metal pattern and a first metal silicide pattern covering a lower surface and a sidewall of the first barrier pattern, and a second contact plug structure extending in the vertical direction on a peripheral circuit region of the substrate and including a second metal pattern and a second barrier pattern covering a lower surface and a sidewall of the second metal pattern.

公开(公告)号：US12016179B2

公开(公告)日：2024-06-18

申请号：US17534528

申请日：2021-11-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Masaaki Higashitani

IPC: H10B43/27 ,  G11C16/10 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H10B43/27 ,  G11C16/10 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7926

Abstract: A memory device includes an alternating stack of insulating layers and control gate layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure containing a memory film and a vertical semiconductor channel located within the memory opening. The memory film contains a resonant tunneling barrier stack, a semiconductor barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the semiconductor barrier layer.

公开(公告)号：US12004352B2

公开(公告)日：2024-06-04

申请号：US18334693

申请日：2023-06-14

Applicant: KIOXIA CORPORATION

Inventor： Takeshi Kamigaichi

IPC: H10B43/27 ,  H01L29/417 ,  H01L29/423 ,  H10B41/27 ,  H10B43/10 ,  H10B43/30 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L29/41741 ,  H01L29/4234 ,  H10B43/10 ,  H10B43/30 ,  H10B43/35 ,  H10B41/27

Abstract: A semiconductor body device includes a stacked body including a plurality of electrode layers stacked with an insulator interposed, a semiconductor body extending in a stacking direction of the stacked body through the electrode layers and having a pipe shape, a plurality of memory cells being provided at intersecting portions of the semiconductor body with the electrode layers, and a columnar insulating member extending in the stacking direction inside the semiconductor body having the pipe shape.

公开(公告)号：US20240155840A1

公开(公告)日：2024-05-09

申请号：US18416095

申请日：2024-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC: H10B43/27 ,  H01L23/498 ,  H01L23/522 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50

CPC classification number: H10B43/27 ,  H01L23/49844 ,  H01L23/5226 ,  H01L23/535 ,  H01L29/408 ,  H01L29/4234 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50 ,  H01L2924/0002

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

公开(公告)号：US20240136419A1

公开(公告)日：2024-04-25

申请号：US17969904

申请日：2022-10-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MAEDA ,  Yoshiyuki KAWASHIMA

IPC: H01L29/423 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/4234 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/788 ,  H01L29/792

Abstract: A height of an upper surface of a control gate electrode is lower than a highest position of a lower surface of a silicide layer on a memory gate electrode adjacent to the control gate electrode via an ONO film. As a result, a structure in contact with the ONO film between the control gate electrode and the memory gate electrode is only the control gate electrode and the memory gate electrode made of polysilicon.

公开(公告)号：US11943924B2

公开(公告)日：2024-03-26

申请号：US17181901

申请日：2021-02-22

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/512 ,  H10B43/35

Abstract: Various embodiments include methods and apparatus having a number of charge trap structures, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric region, the blocking dielectric region located on a charge trap region of the charge trap structure. At least a portion of the gate can be separated by a void from a region which the charge trap structure is directly disposed. Additional apparatus, systems, and methods are disclosed.