公开(公告)号：US20240130124A1

公开(公告)日：2024-04-18

申请号：US18324068

申请日：2023-05-25

申请人： Micron Technology, Inc.

发明人： Shyam Surthi ,  Richard J. Hill ,  Gurtej S. Sandhu ,  Byeung Chul Kim ,  Francois H. Fabreguette ,  Chris M. Carlson ,  Michael E. Koltonski ,  Shane J. Trapp

IPC分类号： H10B43/27

CPC分类号： H10B43/27

摘要： An electronic device comprising a cell region comprising stacks of alternating dielectric materials and conductive materials. A pillar region is adjacent to the cell region and comprises storage node segments adjacent to adjoining oxide materials and adjacent to a tunnel region. The storage node segments are separated by a vertical portion of the tunnel region. A high-k dielectric material is adjacent to the conductive materials of the cell region and to the adjoining oxide materials of the pillar region. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

公开(公告)号：US11925022B2

公开(公告)日：2024-03-05

申请号：US17643040

申请日：2021-12-07

申请人： Micron Technology, Inc.

发明人： Ugo Russo ,  Chris M. Carlson

IPC分类号： H01L27/11582 ,  G11C5/06 ,  H01L21/28 ,  H01L27/1157 ,  H10B43/27 ,  H10B43/35

CPC分类号： H10B43/27 ,  G11C5/063 ,  H10B43/35

摘要： A vertical structure extends through a tiered structure of alternating conductive and insulative materials. The vertical structure includes a channel structure and a tunneling structure. At least one of the conductive materials of the tiered structure provides a select gate tier (e.g., including a control gate for a select gate drain (SGD) transistor). Adjacent the select gate tier of the tiered structure, the tunneling structure consists of or consists essentially of an oxide-only material. Adjacent the word line tiers of the tiered structure, the tunneling structure comprises at least one material that is other than an oxide-only material, such as a nitride or oxynitride. The oxide-only material adjacent the select gate tier may inhibit unintentional loss of charge from a neighboring charge storage structure, which may improve the stability of the threshold voltage (Vth) of the select gate tier.

公开(公告)号：US20220336581A1

公开(公告)日：2022-10-20

申请号：US17739621

申请日：2022-05-09

申请人： Micron Technology, Inc.

发明人： Chris M. Carlson

IPC分类号： H01L29/06 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11582 ,  H01L21/764

摘要： Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a channel to conduct current, the channel including a first channel portion and a second channel portion, a first memory cell structure located between a first gate and the first channel portion, a second memory cell structure located between a second gate and the second channel portion, and a void located between the first and second gates and between the first and second memory cell structures.

公开(公告)号：US11329127B2

公开(公告)日：2022-05-10

申请号：US16863117

申请日：2020-04-30

申请人： Micron Technology, Inc.

发明人： Chris M. Carlson

IPC分类号： H01L29/06 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11582 ,  H01L21/764 ,  G11C16/06 ,  G11C16/04

摘要： Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a channel to conduct current, the channel including a first channel portion and a second channel portion, a first memory cell structure located between a first gate and the first channel portion, a second memory cell structure located between a second gate and the second channel portion, and a void located between the first and second gates and between the first and second memory cell structures.

公开(公告)号：US20220102378A1

公开(公告)日：2022-03-31

申请号：US17643040

申请日：2021-12-07

申请人： Micron Technology, Inc.

发明人： Ugo Russo ,  Chris M. Carlson

IPC分类号： H01L27/11582 ,  H01L27/1157 ,  G11C5/06

摘要： A vertical structure extends through a tiered structure of alternating conductive and insulative materials. The vertical structure includes a channel structure and a tunneling structure. At least one of the conductive materials of the tiered structure provides a select gate tier (e.g., including a control gate for a select gate drain (SGD) transistor). Adjacent the select gate tier of the tiered structure, the tunneling structure consists of or consists essentially of an oxide-only material. Adjacent the word line tiers of the tiered structure, the tunneling structure comprises at least one material that is other than an oxide-only material, such as a nitride or oxynitride. The oxide-only material adjacent the select gate tier may inhibit unintentional loss of charge from a neighboring charge storage structure, which may improve the stability of the threshold voltage (Vth) of the select gate tier.

公开(公告)号：US20220077176A1

公开(公告)日：2022-03-10

申请号：US17013047

申请日：2020-09-04

申请人： Micron Technology, Inc.

发明人： Shyam Surthi ,  Richard J. Hill ,  Gurtej S. Sandhu ,  Byeung Chul Kim ,  Francois H. Fabreguette ,  Chris M. Carlson ,  Michael E. Koltonski ,  Shane J. Trapp

IPC分类号： H01L27/11582

摘要： An electronic device comprising a cell region comprising stacks of alternating dielectric materials and conductive materials. A pillar region is adjacent to the cell region and comprises storage node segments adjacent to adjoining oxide materials and adjacent to a tunnel region. The storage node segments are separated by a vertical portion of the tunnel region. A high-k dielectric material is adjacent to the conductive materials of the cell region and to the adjoining oxide materials of the pillar region. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

公开(公告)号：US10910476B2

公开(公告)日：2021-02-02

申请号：US16589985

申请日：2019-10-01

申请人： Micron Technology, Inc.

发明人： Chris M. Carlson

IPC分类号： H01L21/28

摘要： Some embodiments include an integrated structure having a gallium-containing material between a charge-storage region and a semiconductor-containing channel region. Some embodiments include an integrated structure having a charge-storage region under a conductive gate, a tunneling region under the charge-storage region, and a semiconductor-containing channel region under the tunneling region. The tunneling region includes at least one dielectric material directly adjacent a gallium-containing material. Some embodiments include an integrated structure having a charge-trapping region under a conductive gate, a first oxide under the charge-storage region, a gallium-containing material under the first oxide, a second oxide under the gallium-containing material, and a semiconductor-containing channel region under the second oxide.

公开(公告)号：US10586807B2

公开(公告)日：2020-03-10

申请号：US16437781

申请日：2019-06-11

申请人： Micron Technology, Inc.

发明人： Zhiqiang Xie ,  Chris M. Carlson ,  Justin B. Dorhout ,  Anish A. Khandekar ,  Greg Light ,  Ryan Meyer ,  Kunal R. Parekh ,  Dimitrios Pavlopoulos ,  Kunal Shrotri

IPC分类号： H01L27/11582 ,  H01L21/02 ,  H01L27/11556 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311 ,  H01L27/11565 ,  H01L27/11519

摘要： An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative tiers and wordline tiers. The wordline tiers have terminal ends corresponding to control-gate regions of individual memory cells. The control-gate regions individually comprise part of a wordline in individual of the wordline tiers. A charge-blocking region of the individual memory cells extends elevationally along the individual control-gate regions. Charge-storage material of the individual memory cells extends elevationally along individual of the charge-blocking regions. Channel material extends elevationally along the vertical stack. Insulative charge-passage material is laterally between the channel material and the charge-storage material. Elevationally-extending walls laterally separate immediately-laterally-adjacent of the wordlines. The walls comprise laterally-outer insulative material and silicon-containing material spanning laterally between the laterally-outer insulative material. The silicon-containing material comprises at least 30 atomic percent of at least one of elemental-form silicon or a silicon-containing alloy. Other aspects, including method, are also disclosed.

公开(公告)号：US20200020703A1

公开(公告)日：2020-01-16

申请号：US16580751

申请日：2019-09-24

申请人： Micron Technology, Inc.

发明人： Chris M. Carlson ,  Ugo Russo

IPC分类号： H01L27/1157 ,  H01L29/51 ,  H01L29/423 ,  H01L27/11582 ,  H01L21/28

摘要： Electronic apparatus and methods of forming the electronic apparatus may include one or more charge trap structures for use in a variety of electronic systems and devices, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, a void is located between the charge trap region and a region on which the charge trap structure is disposed. In various embodiments, a tunnel region separating a charge trap region from a semiconductor pillar of a charge trap structure, can be arranged such that the tunnel region and the semiconductor pillar are boundaries of a void. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20190051660A1

公开(公告)日：2019-02-14

申请号：US15675197

申请日：2017-08-11

申请人： Micron Technology, Inc.

发明人： Chris M. Carlson

IPC分类号： H01L27/11582 ,  H01L29/423 ,  H01L21/28

摘要： Various embodiments include methods and apparatus having a number of charge trap structures, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric region, the blocking dielectric region located on a charge trap region of the charge trap structure. At least a portion of the gate can be separated by a void from a region which the charge trap structure is directly disposed. Additional apparatus, systems, and methods are disclosed.