公开(公告)号：US11037956B2

公开(公告)日：2021-06-15

申请号：US16988548

申请日：2020-08-07

申请人： Micron Technology, Inc.

发明人： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Purnima Narayanan ,  Shyam Surthi

IPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L21/02 ,  G11C16/08

摘要： Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220077176A1

公开(公告)日：2022-03-10

申请号：US17013047

申请日：2020-09-04

申请人： Micron Technology, Inc.

发明人： Shyam Surthi ,  Richard J. Hill ,  Gurtej S. Sandhu ,  Byeung Chul Kim ,  Francois H. Fabreguette ,  Chris M. Carlson ,  Michael E. Koltonski ,  Shane J. Trapp

IPC分类号： H01L27/11582

摘要： An electronic device comprising a cell region comprising stacks of alternating dielectric materials and conductive materials. A pillar region is adjacent to the cell region and comprises storage node segments adjacent to adjoining oxide materials and adjacent to a tunnel region. The storage node segments are separated by a vertical portion of the tunnel region. A high-k dielectric material is adjacent to the conductive materials of the cell region and to the adjoining oxide materials of the pillar region. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

公开(公告)号：US11127830B2

公开(公告)日：2021-09-21

申请号：US16251063

申请日：2019-01-17

申请人： Micron Technology, Inc.

发明人： John A. Smythe ,  Silvia Borsari ,  Francois H. Fabreguette ,  Sutharsan Ketharanathan

IPC分类号： H01L29/423 ,  H01L21/311

摘要： Apparatus (e.g., semiconductor devices) include stack structures with at least one conductive region and at least one nonconductive material. A multidielectric spacer is adjacent the at least one conductive region and comprises first and second dielectric materials. The first dielectric material, adjacent the at least one conductive region, includes silicon and nitrogen. The second dielectric material, adjacent the first dielectric material, comprises silicon-carbon bonds and defines a substantially straight, vertical, outer sidewall. In methods to form such apparatus, the first dielectric material may be formed with selectivity on the at least one conductive region, and the second dielectric material may be formulated and formed to exhibit etch resistance.

公开(公告)号：US20200235005A1

公开(公告)日：2020-07-23

申请号：US16251063

申请日：2019-01-17

申请人： Micron Technology, Inc.

发明人： John A. Smythe ,  Silvia Borsari ,  Francois H. Fabreguette ,  Sutharsan Ketharanathan

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L23/532

摘要： Apparatus (e.g., semiconductor devices) include stack structures with at least one conductive region and at least one nonconductive material. A multidielectric spacer is adjacent the at least one conductive region and comprises first and second dielectric materials. The first dielectric material, adjacent the at least one conductive region, includes silicon and nitrogen. The second dielectric material, adjacent the first dielectric material, comprises silicon-carbon bonds and defines a substantially straight, vertical, outer sidewall. In methods to form such apparatus, the first dielectric material may be formed with selectivity on the at least one conductive region, and the second dielectric material may be formulated and formed to exhibit etch resistance.

公开(公告)号：US11631697B2

公开(公告)日：2023-04-18

申请号：US17672659

申请日：2022-02-15

申请人： Micron Technology, Inc.

发明人： Shyam Surthi ,  Byeung Chul Kim ,  Richard J. Hill ,  Francois H. Fabreguette ,  Gurtej S. Sandhu

IPC分类号： H01L27/11582 ,  G11C5/06 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157

摘要： Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. A channel material extends vertically along the stack. The channel material includes a semiconductor composition and has first segments alternating with second segments. The first segments are adjacent the wordline levels and the second segments are adjacent the insulative levels. The first segments have a first dopant distribution and the second segments have a second dopant distribution which is different from the first dopant distribution. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220173123A1

公开(公告)日：2022-06-02

申请号：US17672659

申请日：2022-02-15

申请人： Micron Technology, Inc.

发明人： Shyam Surthi ,  Byeung Chul Kim ,  Richard J. Hill ,  Francois H. Fabreguette ,  Gurtej S. Sandhu

IPC分类号： H01L27/11582 ,  G11C5/06 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157

摘要： Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. A channel material extends vertically along the stack. The channel material includes a semiconductor composition and has first segments alternating with second segments. The first segments are adjacent the wordline levels and the second segments are adjacent the insulative levels. The first segments have a first dopant distribution and the second segments have a second dopant distribution which is different from the first dopant distribution. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210366927A1

公开(公告)日：2021-11-25

申请号：US17393664

申请日：2021-08-04

申请人： Micron Technology, Inc.

发明人： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Shyam Surthi

IPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/792 ,  H01L21/02 ,  H01L29/788

摘要： Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and include second regions proximate to the control gate regions. High-k dielectric structures are directly against the control gate regions and extend entirely across the insulative levels. Charge-blocking material is adjacent to the high-k dielectric structures. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

公开(公告)号：US20210057436A1

公开(公告)日：2021-02-25

申请号：US16548267

申请日：2019-08-22

申请人： Micron Technology, Inc.

发明人： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Shyam Surthi

IPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/788 ,  H01L21/02 ,  H01L29/792

摘要： Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and include second regions proximate to the control gate regions. High-k dielectric structures are directly against the control gate regions and extend entirely across the insulative levels. Charge-blocking material is adjacent to the high-k dielectric structures. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

公开(公告)号：US20200321351A1

公开(公告)日：2020-10-08

申请号：US16374527

申请日：2019-04-03

申请人： Micron Technology, Inc.

发明人： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Purnima Narayanan ,  Shyam Surthi

IPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L21/02 ,  G11C16/08

摘要： Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11557608B2

公开(公告)日：2023-01-17

申请号：US17393664

申请日：2021-08-04

申请人： Micron Technology, Inc.

发明人： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Shyam Surthi

IPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/792 ,  H01L21/02 ,  H01L29/788

摘要： Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and include second regions proximate to the control gate regions. High-k dielectric structures are directly against the control gate regions and extend entirely across the insulative levels. Charge-blocking material is adjacent to the high-k dielectric structures. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.