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公开(公告)号：US20240318524A9
公开(公告)日：2024-09-26
申请号：US17834826
申请日：2022-06-07
IPC分类号： E21B33/13 , E21B29/02 , E21B29/10 , E21B33/12 , E21B36/00 , H01L25/00 , H01L25/065 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11582
CPC分类号： E21B33/13 , E21B29/02 , E21B29/10 , E21B33/12 , E21B36/008 , H01L25/0657 , H01L25/50 , H10B41/27 , H10B43/10 , H10B43/27 , H10B43/35 , H10B43/40 , H01L24/05 , H01L2224/0401
摘要： This disclosure describes a device and method of sealing perforations on a well casing inside a subterranean well. The device comprises a generally cylindrical sleeve having an open top and a closed bottom; a heater located inside the sleeve, the heater comprising a thermite mixture; an ignition mechanism that ignites the thermite mixture upon actuation; and a string connected to the heater ignition and detachably engages the sleeve. The method comprises lowering a body of meltable plugging material into the well casing near the perforations; lowering the plugging device into the well casing immediately on top of the body of meltable plugging material; melting the meltable plugging material by igniting the thermite thereby transferring heat to the body of meltable plugging material; forcing the molten plugging material into the perforations by pushing the plugging tool further downhole; cooling the plugging tool and the plugging material until the plugging material solidifies; disengaging the tubing string from the sleeve and retrieving the tubing string with the heater; and removing the sleeve and bismuth remaining in the well casing, but not in the perforations.
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公开(公告)号：USRE50137E1
公开(公告)日：2024-09-17
申请号：US17586023
申请日：2022-01-27
发明人： Jang-Gn Yun , Zhiliang Xia , Ahn-Sik Moon , Se-Jun Park , Joon-Sung Lim , Sung-Min Hwang
IPC分类号： H01L27/1157 , H01L23/522 , H01L23/528 , H01L27/11565 , H01L27/11582 , H10B43/10 , H10B43/27 , H10B43/35
CPC分类号： H10B43/35 , H01L23/5226 , H01L23/528 , H10B43/10 , H10B43/27
摘要： A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.
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公开(公告)号：US12048152B2
公开(公告)日：2024-07-23
申请号：US17035930
申请日：2020-09-29
发明人： Seokcheon Baek
IPC分类号： H01L27/11582 , G11C8/14 , H01L23/522 , H01L27/11565 , H01L29/423 , H01L29/792 , H10B43/10 , H10B43/27
CPC分类号： H10B43/27 , G11C8/14 , H01L23/5226 , H01L29/4234 , H01L29/7926 , H10B43/10
摘要： A vertical memory device includes a plurality of memory blocks having a plurality of horizontal gate electrodes spaced apart from each other in a first direction and extending in a second direction. A plurality of vertical channels extends through the horizontal gate electrodes in the first direction. A plurality of charge storage structures are disposed between the vertical channels and the horizontal gate electrodes. A conductive path extends in a third direction. The plurality of memory blocks are arranged in the third direction and are divided from each other by a first division pattern that extends in the second direction. The plurality of horizontal gate electrodes at each level are connected to the conductive path at a first lateral side in the second direction to form a shared memory block.
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公开(公告)号：US20240107761A1
公开(公告)日：2024-03-28
申请号：US17968595
申请日：2022-10-18
发明人： Di Wang , Zhong Zhang , Wenxi Zhou , Zhiliang Xia , Zongliang Huo , Wei Xie
IPC分类号： H01L27/11582 , H01L23/528 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157
CPC分类号： H01L27/11582 , H01L23/5283 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157
摘要： In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure are formed. All the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure are replaced with conductive layers. Word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure are formed at different depths, such that the word line pick-up structures are electrically connected to the conductive layers, respectively, in the second region of the stack structure.
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公开(公告)号：US20240081058A1
公开(公告)日：2024-03-07
申请号：US17939762
申请日：2022-09-07
发明人： Yan-Ru Su
IPC分类号： H01L27/11582 , H01L27/11565 , H01L27/11568
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/11568
摘要： A memory device includes a stack structure, a channel pillar, a first conductive pillar, a second conductive pillar, a charge storage structure, a first conductive layer, a second conductive layer, and an insulating liner layer. The stack structure is located on a dielectric substrate and includes gate layers and insulating layers alternately stacked with each other. The channel pillar extends through the stack structure. The first conductive pillar and the second conductive pillar are located in and electrically connecting with the channel pillars. The charge storage structure is located between the gate layers and the channel pillar. The first conductive and the second conductive layers are located between the stack structure and the dielectric substrate. The second conductive layer is closer the channel layer than the first conductive layer. The insulating liner layer separates the second conductive layer from the channel layer and the first conductive layer.
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公开(公告)号：US20240074181A1
公开(公告)日：2024-02-29
申请号：US17896959
申请日：2022-08-26
发明人： Linchun Wu , Kun Zhang , Wenxi Zhou , Cuicui Kong , Shuangshuang Wu , Zhiliang Xia , Zongliang Huo
IPC分类号： H01L27/11582 , H01L23/528 , H01L27/11519 , H01L27/11556 , H01L27/11565
CPC分类号： H01L27/11582 , H01L23/5283 , H01L27/11519 , H01L27/11556 , H01L27/11565
摘要： A memory device includes a stack structure, channel structures, and a slit structure. The stack structure includes interleaved conductive layers and dielectric layers, and the conductive layers include a plurality of word lines. Each of the channel structures extends vertically through the stack structure. The slit structure extends vertically through the stack structure. An outer region of the stack structure includes a staircase structure, and the interleaved conductive layers and dielectric layers in a bottom portion of the stack structure are wider than the interleaved conductive layers and dielectric layers in a top portion of the stack structure. A first outer width of the slit structure in the bottom portion of the stack structure is greater than a second outer width of the slit structure in the top portion of the stack structure.
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7.发明公开公开(公告)号：US20240074170A1
公开(公告)日：2024-02-29
申请号：US17823639
申请日：2022-08-31
发明人： Takashi YUDA , Noriyuki NAGAHATA , Ippei YASUDA
IPC分类号： H01L27/11556 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L27/1157 , H01L27/11582
CPC分类号： H01L27/11556 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L27/1157 , H01L27/11582
摘要： A memory device includes an alternating stack of insulating layers and electrically conductive layers arranged along a vertical direction, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory film. The memory film includes a blocking dielectric film, a tunneling dielectric layer and a vertical stack of memory elements located between the blocking dielectric film and the tunneling dielectric layer. The blocking dielectric film includes component layers which include, from a side that is proximal to the vertical stack of memory elements toward a side that is distal from the vertical stack of memory elements, an inner silicon oxide blocking dielectric layer, a middle dielectric metal oxide blocking dielectric layer, an outer silicon oxide blocking dielectric layer, and an outer dielectric metal oxide blocking dielectric layer.
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公开(公告)号：US20240071902A1
公开(公告)日：2024-02-29
申请号：US17893718
申请日：2022-08-23
发明人： Shuangqiang Luo , Lifang Xu
IPC分类号： H01L23/522 , H01L21/768 , H01L27/11519 , H01L27/11524 , H01L27/11551 , H01L27/11565 , H01L27/1157 , H01L27/11578
CPC分类号： H01L23/5226 , H01L21/76877 , H01L27/11519 , H01L27/11524 , H01L27/11551 , H01L27/11565 , H01L27/1157 , H01L27/11578
摘要： Methods, systems, and devices for folded staircase via routing for memory are described. For instance, a memory device may include a set of word lines extending in first direction. Additionally, the memory device may include a first via, a second via, and a third via in a trench that extends through at least a portion of the set of word lines The first via, the second via, and the third via may extend in a second direction different than the first, where the second via is between the first via and the third via along the first direction, and where the second via is coupled with a word line of the set of word lines. Additionally, the first via and the third via may be electrically isolated from the word line of the set of word lines.
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公开(公告)号：US20240029795A1
公开(公告)日：2024-01-25
申请号：US17868232
申请日：2022-07-19
IPC分类号： G11C16/04 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582
CPC分类号： G11C16/0483 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582
摘要： Memory circuitry comprising strings of memory cells comprises channel-material strings of memory cells extending through insulative tiers and conductive tiers in a memory-array region. The insulative and conductive tiers extend from the memory-array region into a stair-step region. A plurality of stair-step structures is in the stair-step region. The stair-step structures individually comprise two opposing flights of stairs. The stair-step structures comprise an SGD stair-step structure and non-SGD stair-step structures. At least one of the non-SGD stair-step structures has less total stairs than are in individual of multiple others of the non-SGD stair-step structures. Other embodiments, including method, are disclosed.
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10.发明公开公开(公告)号：US20240015960A1
公开(公告)日：2024-01-11
申请号：US17857375
申请日：2022-07-05
发明人： Hiroaki Namba
IPC分类号： H01L27/11556 , H01L23/522 , H01L23/528 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L27/1157 , H01L27/11582
CPC分类号： H01L27/11556 , H01L23/5226 , H01L23/5283 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L27/1157 , H01L27/11582
摘要： A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers that is located on a front side of at least one semiconductor material layer; memory openings vertically extending through the alternating stack; memory opening fill structures; a dielectric material portion contacting sidewalls of the insulating layers of the alternating stack. In one embodiment, a connection via structure can vertically extend through the dielectric material portion, and a metal plate can contact the connection via structure. Alternately or additionally, an integrated via and pad structure may be provided, which includes a conductive via portion vertically extending through the dielectric material portion and a conductive pad portion located on an end of the conductive via portion.
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