公开(公告)号：US20240071496A1

公开(公告)日：2024-02-29

申请号：US17897460

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs extending along a first direction. Multiple different-depth and height-sequential treads in individual of the stairs extend along a second direction that is orthogonal to the first direction. Individual of the multiple different-depth treads comprise conducting material of one of the conductive tiers. The cavity comprises a pair of laterally-opposing outermost sidewalls relative to the second direction and that individually extend along the first direction. The multiple different-depth and height-sequential treads in the individual stairs comprise a single flight of said treads that extends along the second direction from one of the laterally-opposing outermost sidewalls to the other of the laterally-opposing outermost sidewalls. Methods are disclosed.

公开(公告)号：US20240032294A1

公开(公告)日：2024-01-25

申请号：US17813818

申请日：2022-07-20

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

Abstract: An electronic device comprising a source stack comprising one or more conductive materials, and an oxide fill region within an upper portion of the source stack. A source contact is adjacent to the source stack and the oxide fill region, and a doped semiconductive material is adjacent to the source contact. Tiers of alternating conductive materials and dielectric materials are adjacent to the doped semiconductive material, and pillars extend through the tiers, the doped semiconductive material, and the source contact and into the source stack. Additional electronic devices are also disclosed, as are related methods and electronic systems.

公开(公告)号：US20230413551A1

公开(公告)日：2023-12-21

申请号：US17807819

申请日：2022-06-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yao CHEN ,  Shigehisa INOUE ,  Kazuto OHSAWA ,  Hisaya SAKAI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/522 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11519

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L23/5226 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11524 ,  H01L23/5283

Abstract: A memory die includes first and second memory-region alternating stacks of memory-region insulating layers and electrically conductive layers that are laterally spaced apart from each other by a respective first portion of a retro-stepped dielectric structure overlying first stepped surfaces of the first and second memory-region alternating stacks, memory opening fill structures located the first and second memory-region alternating stacks, and a peripheral alternating stack of peripheral insulating layers and spacer material which is laterally spaced from the second memory-region alternating stack by a second portion of the retro-stepped dielectric structure overlying second stepped surfaces of the second memory-region alternating stack. Bottom surfaces of the first and second memory-region alternating stacks are spaced apart by a first lateral spacing distance, and bottom surfaces of the second memory alternating stack and the peripheral alternating stack are spaced apart by the first lateral spacing distance.

公开(公告)号：US20230397421A1

公开(公告)日：2023-12-07

申请号：US17876271

申请日：2022-07-28

Applicant: Micron Technology, Inc.

Inventor： Mallesh Rajashekharaiah ,  Lifang Xu ,  Nancy M. Lomeli

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another, the tiers including conductive materials that form part of respective control gates for memory cells of the apparatus; a staircase structure formed in the tiers, the conductive materials including respective portions that collectively form a part of the staircase structure, the staircase structure including a sidewall on a side of the staircase structure; a dielectric liner formed on the sidewall; recesses formed in respective tiers and adjacent the sidewall such that respective portions of the dielectric liner are located in the recesses; and a contact structure extending through a portion of the dielectric liner, wherein the portions of the dielectric liner are between the contract structure and the conductive materials.

公开(公告)号：US20230369141A1

公开(公告)日：2023-11-16

申请号：US17974205

申请日：2022-10-26

Applicant: SK hynix Inc.

Inventor： Jae Ho KIM

IPC: H01L21/66 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417

CPC classification number: H01L22/32 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/41775 ,  H01L23/53266

Abstract: A method of manufacturing a semiconductor device includes forming a test circuit in a cross area of a scribe lane area disposed between chip areas of a substrate. The method also includes forming a first dummy structure on the test circuit, forming a test pad in a line area of the scribe lane area of the substrate, and cutting the substrate along the scribe lane area.

公开(公告)号：US20230363160A1

公开(公告)日：2023-11-09

申请号：US17737771

申请日：2022-05-05

Applicant: MACRONIX International Co., Ltd.

Inventor： Meng-Yen Wu ,  Pi-Shan Tseng

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L23/528 ,  H01L23/522 ,  H01L23/04

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L23/5283 ,  H01L23/5226 ,  H01L23/04

Abstract: A memory device may be applicated in a 3D AND flash memory device. The memory device includes a dielectric substrate, a plurality of memory cells, a slit structure, and a middle section of a seal ring. The gate composite stack structure disposed on the dielectric substrate in a first region and a second region of the dielectric substrate. The plurality of memory cells disposed in the composite stack structure. The slit structure extends through the composite stack structure in first region. The composite stack structure is divided into a plurality of blocks. The middle section of a seal ring extends through the composite stack structure in the second region. The middle section of the seal ring includes a body part extending through the composite stack structure in the second region and a liner layer located between the body part and the composite stack structure.

公开(公告)号：US20230352091A1

公开(公告)日：2023-11-02

申请号：US17734623

申请日：2022-05-02

Applicant: Micron Technology, Inc.

Inventor： Jun Fujiki ,  Yoshiaki Fukuzumi ,  Akira Goda

IPC: G11C16/08 ,  G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: G11C16/08 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another, each of the tiers including memory cells and a control gate for the memory cells, each of the tiers including first transistors connected in series between the control gate in a respective tier and a conductive line, and second transistors connected in series between the control gate in the respective tier and the conductive line, the second transistors connected in parallel with the first transistors between the control gate and the conductive line, conductive joints coupled to channel regions of the first and second transistors, and gates for the first transistors and second transistors, each of the gates shared by one of the first transistors and one of the second transistors.

公开(公告)号：US20230343696A1

公开(公告)日：2023-10-26

申请号：US17725015

申请日：2022-04-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Inventor： Gerben Doornbos ,  Mauricio Manfrini

IPC: H01L23/522 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L23/5226 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42336 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66833

Abstract: A semiconductor device is provided. The semiconductor device includes a memory structure including a first transistor channel, a gate structure overlying the first transistor channel, and a second transistor channel overlying the gate structure. The gate structure includes a control gate.

公开(公告)号：US20230343394A1

公开(公告)日：2023-10-26

申请号：US17727515

申请日：2022-04-22

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  Jordan D. Greenlee ,  John D. Hopkins

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528

CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L23/5226 ,  H01L23/5283

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to conductor material of the conductor tier. Below the stack, an insulating tier is directly above the conductor tier and a metal-material tier is directly above the insulating tier. Conductive rings extend through the metal-material tier and the insulating tier to conductor material of the conductor tier. The conductive rings individually are around individual horizontal locations directly above which are individual of the channel-material strings. The channel-material strings directly electrically couple to the conductor material of the conductor tier through the insulating tier by the conductive rings. Other embodiments, including method, are disclosed.

公开(公告)号：US20230337427A1

公开(公告)日：2023-10-19

申请号：US17842259

申请日：2022-06-16

Applicant: SK hynix Inc.

Inventor： Jae Ho KIM

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

Abstract: A semiconductor device includes: a stack including a first plane edge region, a second plane edge region, and a contact region located between the first plane edge region and the second plane edge region; and a first insulating structure including a first portion located in the first plane edge region of the stack, a second portion located in the second plane edge region of the stack, and a third portion located in the contact region of the stack, wherein the first portion includes a first curved edge.