公开(公告)号：US20240196619A1

公开(公告)日：2024-06-13

申请号：US18581037

申请日：2024-02-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ryo KAMBAYASHI ,  Kazuto OHSAWA

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A three dimensional memory device includes: an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, and a backside trench fill structure that includes a backside trench insulating spacer and a backside contact via structure. The backside contact via structure includes a first metallic nitride liner including a nitride of a first metal, a first metal core fill conductive material portion include a second metal, and a second metallic nitride liner including a nitride of the second metal located between an inner sidewall of the first metallic nitride liner and an outer sidewall of the first metal core fill conductive material portion.

公开(公告)号：US20210210428A1

公开(公告)日：2021-07-08

申请号：US17155512

申请日：2021-01-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kazuto OHSAWA ,  Kota FUNAYAMA ,  Hisaya SAKAI ,  Yoshitaka OTSU

IPC: H01L23/522 ,  H01L27/11556 ,  H01L27/11582

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, a finned dielectric moat structure including a dielectric core portion vertically extending through each layer within the alternating stack and a vertical stack of dielectric fin portions laterally extending outward from the dielectric core portion, a vertical stack of insulating plates and dielectric material plates laterally surrounded by the finned dielectric moat structure, and an interconnection via structure vertically extending through the vertical stack and contacting a top surface of an underlying metal interconnect structure.

公开(公告)号：US20230413551A1

公开(公告)日：2023-12-21

申请号：US17807819

申请日：2022-06-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yao CHEN ,  Shigehisa INOUE ,  Kazuto OHSAWA ,  Hisaya SAKAI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/522 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11519

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L23/5226 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11524 ,  H01L23/5283

Abstract: A memory die includes first and second memory-region alternating stacks of memory-region insulating layers and electrically conductive layers that are laterally spaced apart from each other by a respective first portion of a retro-stepped dielectric structure overlying first stepped surfaces of the first and second memory-region alternating stacks, memory opening fill structures located the first and second memory-region alternating stacks, and a peripheral alternating stack of peripheral insulating layers and spacer material which is laterally spaced from the second memory-region alternating stack by a second portion of the retro-stepped dielectric structure overlying second stepped surfaces of the second memory-region alternating stack. Bottom surfaces of the first and second memory-region alternating stacks are spaced apart by a first lateral spacing distance, and bottom surfaces of the second memory alternating stack and the peripheral alternating stack are spaced apart by the first lateral spacing distance.

公开(公告)号：US20230309298A1

公开(公告)日：2023-09-28

申请号：US17654465

申请日：2022-03-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kazuto OHSAWA

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  G11C16/04 ,  H01L23/522

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L23/5226 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers. Stepped surfaces including vertical sidewalls of the insulating layers are present in a staircase region. Pad stacks are located on the stepped surfaces. Each of the pad stacks includes an insulating pad having a same material composition as the insulating layers, and a dielectric material pad having a different material composition than the insulating layers and having sidewalls that are vertically coincident with sidewalls of the insulating pad. Memory stack structures extend through the alternating stack. Each of the memory stack structures includes a vertical stack of memory elements and a vertical semiconductor channel.