公开(公告)号：US20240355396A1

公开(公告)日：2024-10-24

申请号：US18686598

申请日：2022-08-25

申请人： Beijing PXMicro Technology Co. Ltd.

发明人： Jiayong Jiang ,  Zhendong Shi

IPC分类号： G11C16/14 ,  G11C16/04 ,  H01L29/66 ,  H01L29/788 ,  H10B41/27

CPC分类号： G11C16/14 ,  G11C16/0483 ,  H01L29/66825 ,  H01L29/788 ,  H10B41/27

摘要： Provided are a flash memory cell and associated manufacturing, writing, and erasing methods. The flash memory cell comprises a substrate with a deep well region and a well region on which a first and second storage transistor are provided to store separate data and a gating transistor provided horizontally between them to perform a gating operation. The three transistors are connected in series, with a source region of the first storage transistor and a drain region of the second storage transistor connected to separate electrodes of the flash memory cell. The storage transistors have a gate structure composed vertically of a channel region, a gate dielectric stack, a gate electrode, and a hard mask blocking portion. The writing method uses low operation power and fast programming to increase write throughput. The erasing method uses a combined tunneling mechanism to enable low operation power, fast erasing, and improved storage reliability.

公开(公告)号：US20240339546A1

公开(公告)日：2024-10-10

申请号：US18749739

申请日：2024-06-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

发明人： Chin-Yi HUANG ,  Wade SHIH

IPC分类号： H01L29/788 ,  G11C8/14 ,  H01L21/28 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H10B41/10 ,  H10B41/35

CPC分类号： H01L29/788 ,  G11C8/14 ,  H01L29/40114 ,  H01L29/402 ,  H01L29/42324 ,  H01L29/66825 ,  H10B41/10 ,  H10B41/35

摘要： A semiconductor device includes a channel region between a source region and a drain region, a gate over the channel region, a dielectric layer over the gate, a capacitive field plate over the dielectric layer, and a word line electrically coupled to the capacitive field plate.

公开(公告)号：US12101931B2

公开(公告)日：2024-09-24

申请号：US18354881

申请日：2023-07-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wen-Tuo Huang ,  Ping-Cheng Li ,  Hung-Ling Shih ,  Po-Wei Liu ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair ,  Chia-Sheng Lin ,  Shih Kuang Yang

IPC分类号： H10B41/30 ,  H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788

CPC分类号： H10B41/30 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53271 ,  H01L29/401 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/788

摘要： Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

公开(公告)号：US20240222525A1

公开(公告)日：2024-07-04

申请号：US18149868

申请日：2023-01-04

申请人： Winbond Electronics Corp.

发明人： Chung-Hsien LIU

IPC分类号： H01L29/788 ,  H01L21/762 ,  H01L29/66

CPC分类号： H01L29/788 ,  H01L21/76224 ,  H01L29/66825

摘要： A semiconductor structure is provided. The semiconductor structure includes a substrate with a trench between active regions, a tunneling dielectric layer disposed on the substrate, a floating gate layer disposed on the tunneling dielectric layer, and an isolation feature disposed in the trench and on the substrate. The isolation feature has a first opening and a second opening below the first opening. The semiconductor structure further includes a mask disposed on the sidewall of the first opening, and a dielectric stack layer disposed directly above the mask and the second opening.

公开(公告)号：US12027581B2

公开(公告)日：2024-07-02

申请号：US17866772

申请日：2022-07-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Gulbagh Singh ,  Kun-Tsang Chuang ,  Hsin-Chi Chen

IPC分类号： H01L29/94 ,  H01L29/06 ,  H01L29/66 ,  H01L29/76 ,  H01L29/788 ,  H10B41/35

CPC分类号： H01L29/0649 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/788 ,  H10B41/35

摘要： A semiconductor device includes a substrate, a gate oxide layer formed on the substrate, a gate formed on the gate oxide layer, and a spacer formed adjacent the gate and over the substrate. The spacer includes a void filled with air to prevent leakage of charge to and from the gate, thereby reducing data loss and providing better memory retention. The reduction in charge leakage results from reduced parasitic capacitances, fringing capacitances, and overlap capacitances due to the low dielectric constant of air relative to other spacer materials. The spacer can include multiple layers such as oxide and nitride layers. In some embodiments, the semiconductor device is a multiple-time programmable (MTP) memory device.

公开(公告)号：US12015056B2

公开(公告)日：2024-06-18

申请号：US18306359

申请日：2023-04-25

申请人： International Business Machines Corporation

发明人： Yulong Li ,  Paul M. Solomon ,  Siyuranga Koswatta

IPC分类号： H01L29/10 ,  H01L21/28 ,  H01L29/06 ,  H01L29/165 ,  H01L29/205 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/68 ,  H01L29/78 ,  H01L29/788 ,  H01L29/80 ,  H10B12/00 ,  H10B41/30 ,  H10B51/30 ,  H10B63/00

CPC分类号： H01L29/1045 ,  H01L29/0646 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/205 ,  H01L29/40111 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/4983 ,  H01L29/516 ,  H01L29/66431 ,  H01L29/66659 ,  H01L29/66977 ,  H01L29/685 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/802 ,  H10B12/30 ,  H10B41/30 ,  H10B51/30 ,  H10B63/00 ,  H01L29/66825 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/788

摘要： A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.

公开(公告)号：US11880602B2

公开(公告)日：2024-01-23

申请号：US17562783

申请日：2021-12-27

申请人： Huawei Technologies Co., Ltd.

发明人： Meng Zhou ,  Jianhua Zhou

IPC分类号： G06F3/00 ,  G06F3/06 ,  G11C11/56 ,  G11C16/10 ,  G11C16/04 ,  H01L29/788

CPC分类号： G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/0483 ,  H01L29/788

摘要： A data writing method includes: receiving a write command, where the write command carries a type of to-be-written data; determining, based on the type of to-be-written data, a type of storage area that is in an SSD and into which the to-be-written data is written, where the SSD includes a plurality of types of storage areas; determining, based on the type of storage area, a target storage area into which the to-be-written data is written; and writing the to-be-written data into the target storage area. In embodiments of this application, data processing efficiency can be improved.

公开(公告)号：US20230389309A1

公开(公告)日：2023-11-30

申请号：US18447965

申请日：2023-08-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yen-Jou WU ,  Hsin-Hui Lin ,  Yu-Liang Wang ,  Chih-Ming Lee ,  Keng-Ying Liao ,  Ping-Pang Hsieh ,  Su-Yu Yeh

IPC分类号： H10B41/35 ,  H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  G11C8/14 ,  H10B41/10

CPC分类号： H10B41/35 ,  H01L29/788 ,  H10B41/10 ,  H01L29/66825 ,  G11C8/14 ,  H01L29/42324

摘要： The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.

公开(公告)号：US20230363155A1

公开(公告)日：2023-11-09

申请号：US18354881

申请日：2023-07-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wen-Tuo Huang ,  Ping-Cheng Li ,  Hung-Ling Shih ,  Po-Wei Liu ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair ,  Chia-Sheng Lin ,  Shih Kuang Yang

IPC分类号： H10B41/30 ,  H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788

CPC分类号： H10B41/30 ,  H01L29/40114 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53271 ,  H01L29/401 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/788

摘要： Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

公开(公告)号：US20230345717A1

公开(公告)日：2023-10-26

申请号：US18344161

申请日：2023-06-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hung-Ling Shih ,  Yong-Shiuan Tsair

IPC分类号： H01L29/423 ,  H10B41/30 ,  H01L23/528 ,  H01L23/522 ,  H01L29/08 ,  H01L29/66 ,  H01L21/311 ,  G11C29/14 ,  H10B41/42 ,  H01L21/28 ,  H01L29/788 ,  H01L21/3213

CPC分类号： H10B41/42 ,  G11C29/14 ,  H01L21/31116 ,  H01L21/32137 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/0847 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H10B41/30 ,  H01L29/66545

摘要： Various embodiments of the present application are directed to a method for forming an integrated circuit (IC) comprising forming a multilayer film to form a plurality of memory cell structures disposed over a substrate and a plurality of memory test structures next to the memory cell structures. A memory test structure comprises a dummy control gate separated from the substrate by a dummy floating gate. The method further comprises forming a conductive floating gate test contact via along sidewalls of the dummy control gate and the dummy floating gate.