Provided are a flash memory cell and associated manufacturing, writing, and erasing methods. The flash memory cell comprises a substrate with a deep well region and a well region on which a first and second storage transistor are provided to store separate data and a gating transistor provided horizontally between them to perform a gating operation. The three transistors are connected in series, with a source region of the first storage transistor and a drain region of the second storage transistor connected to separate electrodes of the flash memory cell. The storage transistors have a gate structure composed vertically of a channel region, a gate dielectric stack, a gate electrode, and a hard mask blocking portion. The writing method uses low operation power and fast programming to increase write throughput. The erasing method uses a combined tunneling mechanism to enable low operation power, fast erasing, and improved storage reliability.