公开(公告)号：US12167594B2

公开(公告)日：2024-12-10

申请号：US16989778

申请日：2020-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Chin Liu ,  Wei Cheng Wu ,  Yi Hsien Lu ,  Yu-Hsiung Wang ,  Juo-Li Yang

IPC: H01L21/82 ,  G11C16/04 ,  G11C16/12 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/788 ,  H10B10/00 ,  H10B41/42 ,  H10B41/49 ,  H10B41/50 ,  H10B99/00

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

公开(公告)号：US20240381636A1

公开(公告)日：2024-11-14

申请号：US18196730

申请日：2023-05-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chih-Ching LIN

IPC: H10B41/42

Abstract: A semiconductor device includes a substrate, a first film stack, a second film stack, a first gate spacer, a buffer layer, and a second gate spacer. The first and second film stacks are located on the substrate, and are respectively located in an array area and a periphery area. The first gate spacer includes a first portion on a sidewall of the first film stack and a second portion on a sidewall of the second film stack. The buffer layer includes a first portion on a sidewall of the first portion of the first gate spacer and a second portion on a sidewall of the second portion of the first gate spacer. The second gate spacer includes a first portion on a sidewall of the first portion of the buffer layer and a second portion on a sidewall the second portion of the buffer layer.

公开(公告)号：US12075618B2

公开(公告)日：2024-08-27

申请号：US17133395

申请日：2020-12-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Toan Le ,  Nghia Le ,  Hien Pham

IPC: H10B41/42 ,  G06N3/08 ,  G11C16/04 ,  H01L29/788

CPC classification number: H10B41/42 ,  G06N3/08 ,  G11C16/0425 ,  H01L29/7883

Abstract: Numerous embodiments for reading or verifying a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one embodiment, an input comprises a set of input bits that result in a series of input signals applied to a terminal of the selected memory cell, further resulting in a series of output signals that are digitized, shifted based on the bit location of the corresponding input bit in the set of input bits, and added to yield an output indicating a value stored in the selected memory cell.

公开(公告)号：US20240188289A1

公开(公告)日：2024-06-06

申请号：US18404204

申请日：2024-01-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Josh Lin ,  Chia-Ta Hsieh ,  Chen-Ming Huang ,  Chi-Wei Ho

IPC: H10B41/30 ,  H01L21/768 ,  H01L23/485 ,  H01L29/423 ,  H01L29/66 ,  H10B41/10 ,  H10B41/40 ,  H10B41/42

CPC classification number: H10B41/30 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76877 ,  H01L29/42324 ,  H01L29/6653 ,  H10B41/10 ,  H10B41/40 ,  H10B41/42 ,  H01L23/485 ,  H01L29/6656

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a first conductive structure over a substrate. A first intermediate sidewall spacer is formed to surround the first conductive structure. A masking material is formed over the substrate and around the first intermediate sidewall spacer. A part of the first intermediate sidewall spacer protrudes outward from the masking material. The part of the first intermediate sidewall spacer that protrudes outward from the masking material is etched to form a first sidewall spacer.

公开(公告)号：US20240147717A1

公开(公告)日：2024-05-02

申请号：US18491226

申请日：2023-10-20

Applicant: WINBOND ELECTRONICS CORP.

Inventor： Hsin-Hung CHOU ,  Cheng-Shuai LI ,  Kao-Tsair TSAI

IPC: H10B41/42 ,  H10B43/40

CPC classification number: H10B41/42 ,  H10B43/40

Abstract: A pick-up structure of a memory device and a method of manufacturing the memory device are provided. The pick-up structure includes pick-up electrode stripes. Each pickup electrode stripe includes a main body portion in the peripheral pick-up region and an extending portion extending from the main body portion to the memory cell region. The extending portion is narrower than the main body portion. The sidewall surface of the extending portion is aligned with the sidewall surface of the main body portion.

公开(公告)号：US20230345717A1

公开(公告)日：2023-10-26

申请号：US18344161

申请日：2023-06-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Ling Shih ,  Yong-Shiuan Tsair

IPC: H01L29/423 ,  H10B41/30 ,  H01L23/528 ,  H01L23/522 ,  H01L29/08 ,  H01L29/66 ,  H01L21/311 ,  G11C29/14 ,  H10B41/42 ,  H01L21/28 ,  H01L29/788 ,  H01L21/3213

CPC classification number: H10B41/42 ,  G11C29/14 ,  H01L21/31116 ,  H01L21/32137 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/0847 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H10B41/30 ,  H01L29/66545

Abstract: Various embodiments of the present application are directed to a method for forming an integrated circuit (IC) comprising forming a multilayer film to form a plurality of memory cell structures disposed over a substrate and a plurality of memory test structures next to the memory cell structures. A memory test structure comprises a dummy control gate separated from the substrate by a dummy floating gate. The method further comprises forming a conductive floating gate test contact via along sidewalls of the dummy control gate and the dummy floating gate.

公开(公告)号：US12190981B2

公开(公告)日：2025-01-07

申请号：US17866558

申请日：2022-07-18

Applicant: Winbond Electronics Corp.

Inventor： Yao-Ting Tsai ,  Che-Fu Chuang

IPC: G11C8/12 ,  G11C5/06 ,  G11C29/00 ,  G11C29/24 ,  G11C29/52 ,  H10B41/10 ,  H10B41/42 ,  G11C8/14

Abstract: A memory array is provided. The memory array includes multiple memory blocks, each including multiple data storage regions and multiple groups of word lines. Each group of word lines extend across one of the memory blocks. The groups of word lines are connected to multiple overlying signal lines through multiple groups of first word line contact regions in the memory blocks and multiple second word line contact regions between the memory blocks.

公开(公告)号：US12183833B2

公开(公告)日：2024-12-31

申请号：US17592832

申请日：2022-02-04

Applicant: Winbond Electronics Corp.

Inventor： Cheng-Ta Yang ,  Lu-Ping Chiang

IPC: H01L21/00 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30 ,  H10B41/40 ,  H10B41/42 ,  H10B41/49

Abstract: A flash memory device is provided. The flash memory device includes a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, a first polycrystalline silicon layer and a second polycrystalline silicon layer. The first dielectric layer is formed on the substrate located in a first region of a peripheral region, the second dielectric layer is formed on the substrate located in a second region of the peripheral region, and the third dielectric layer is formed on the substrate located in an array region. A bottom surface of the third dielectric layer is lower than a bottom surface of the second dielectric layer. The first polycrystalline silicon layer is formed on the first and the second dielectric layers. The second polycrystalline silicon layer is formed on the third dielectric layer.

公开(公告)号：US20240172434A1

公开(公告)日：2024-05-23

申请号：US18429264

申请日：2024-01-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hsuan Liu ,  Chiang-Ming Chuang ,  Chih-Ming Lee ,  Kun-Tsang Chuang ,  Hung-Che Liao ,  Chia-Ming Pan ,  Hsin-Chi Chen

IPC: H10B41/30 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H10B41/10 ,  H10B41/42 ,  H10B41/47

CPC classification number: H10B41/30 ,  H01L21/32135 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/10 ,  H10B41/42 ,  H10B41/47

Abstract: A semiconductor device includes a stacked gate structure, a plurality of stacks and a first conductive layer. The stacks are disposed aside the stacked gate structure and arranged along both a first direction and a second direction perpendicular to the first direction, wherein the stacks are extended continuously along the first direction and segmented in the second direction. The first conductive layer is disposed between segmented portions of the stacks along the second direction, wherein top surfaces of the segmented portions of the stacks are higher than a top surface of the first conductive layer.

公开(公告)号：US11943921B2

公开(公告)日：2024-03-26

申请号：US17874416

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H10B41/44 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30 ,  H10B41/35 ,  H10B41/41 ,  H10B41/42 ,  H10B43/40

CPC classification number: H10B41/44 ,  H01L21/0276 ,  H01L21/28035 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/76802 ,  H01L29/0847 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/788 ,  H10B41/30

Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. Each memory cell structure of the plurality of memory cell structures comprises a control gate electrode disposed over the substrate, a select gate electrode disposed on one side of the control gate electrode, and a spacer between the control gate electrode and the select gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with a sidewall surface of the select gate electrode within the memory region. A lower inter-layer dielectric layer is disposed on the CESL between the plurality of memory cell structures within the memory region.