公开(公告)号：US11943921B2

公开(公告)日：2024-03-26

申请号：US17874416

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H10B41/44 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30 ,  H10B41/35 ,  H10B41/41 ,  H10B41/42 ,  H10B43/40

CPC classification number: H10B41/44 ,  H01L21/0276 ,  H01L21/28035 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/76802 ,  H01L29/0847 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/788 ,  H10B41/30

Abstract: Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. Each memory cell structure of the plurality of memory cell structures comprises a control gate electrode disposed over the substrate, a select gate electrode disposed on one side of the control gate electrode, and a spacer between the control gate electrode and the select gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with a sidewall surface of the select gate electrode within the memory region. A lower inter-layer dielectric layer is disposed on the CESL between the plurality of memory cell structures within the memory region.

公开(公告)号：US11825651B2

公开(公告)日：2023-11-21

申请号：US17135744

申请日：2020-12-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei Cheng Wu ,  Li-Feng Teng

IPC: H01L29/423 ,  H10B41/42 ,  H10B41/35 ,  H01L21/28 ,  H10B41/30 ,  H10B41/44 ,  H10B41/47 ,  H10B41/48 ,  H10B43/30 ,  H01L29/66

CPC classification number: H10B41/42 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66545 ,  H10B41/30 ,  H10B41/35 ,  H10B41/44 ,  H10B41/47 ,  H10B41/48 ,  H10B43/30

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

公开(公告)号：US20240365542A1

公开(公告)日：2024-10-31

申请号：US18764868

申请日：2024-07-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Cheng WU ,  Li-Feng TENG

IPC: H10B41/42 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H10B41/30 ,  H10B41/35 ,  H10B41/44 ,  H10B41/47 ,  H10B41/48 ,  H10B43/30

CPC classification number: H10B41/42 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66545 ,  H10B41/30 ,  H10B41/35 ,  H10B41/44 ,  H10B41/47 ,  H10B41/48 ,  H10B43/30

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer, and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

公开(公告)号：US12058856B2

公开(公告)日：2024-08-06

申请号：US18231427

申请日：2023-08-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei Cheng Wu ,  Li-Feng Teng

IPC: H10B41/42 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H10B41/30 ,  H10B41/35 ,  H10B41/44 ,  H10B41/47 ,  H10B41/48 ,  H10B43/30

CPC classification number: H10B41/42 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66545 ,  H10B41/30 ,  H10B41/35 ,  H10B41/44 ,  H10B41/47 ,  H10B41/48 ,  H10B43/30

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

公开(公告)号：US11839076B2

公开(公告)日：2023-12-05

申请号：US17472912

申请日：2021-09-13

Applicant: Winbond Electronics Corp.

Inventor： Che-Fu Chuang ,  Hsiu-Han Liao

IPC: H10B41/47 ,  H10B41/46 ,  H10B41/44

CPC classification number: H10B41/47 ,  H10B41/46 ,  H10B41/44

Abstract: A method of forming a semiconductor structure includes forming first to third sacrificial layers on a substrate including a memory cell area and a peripheral area with a word line area. The second and third sacrificial layers in the word line area are removed to expose the top surface of the first sacrificial layer. The first sacrificial layer in the word line area and the third sacrificial layer in the memory cell area are removed. A word line dielectric layer and a first conductive layer are formed on the substrate in the word line area. The first and second sacrificial layers in the memory cell area are removed. A tunneling dielectric layer is formed on the substrate in the memory cell area. The thickness of the tunneling dielectric layer is smaller than the thickness of the word line dielectric layer.

公开(公告)号：US20230380155A1

公开(公告)日：2023-11-23

申请号：US18231427

申请日：2023-08-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei Cheng WU ,  Li-Feng TENG

IPC: H10B41/42 ,  H01L29/423 ,  H01L21/28 ,  H10B41/30 ,  H10B41/35 ,  H10B41/44 ,  H10B41/47 ,  H10B41/48 ,  H10B43/30 ,  H01L29/66

CPC classification number: H10B41/42 ,  H01L29/42344 ,  H01L29/40114 ,  H10B41/30 ,  H10B41/35 ,  H10B41/44 ,  H10B41/47 ,  H10B41/48 ,  H10B43/30 ,  H01L29/42328 ,  H01L29/66545

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

公开(公告)号：US12225723B2

公开(公告)日：2025-02-11

申请号：US17709370

申请日：2022-03-30

Applicant: IOTMEMORY TECHNOLOGY INC.

Inventor： Der-Tsyr Fan ,  I-Hsin Huang ,  Tzung-Wen Cheng

IPC: H10B41/44 ,  H10B41/10 ,  H10B41/48

Abstract: A non-volatile memory device includes at least one memory cell, and the at least one memory cell includes a substrate, a stacked structure, a tunneling dielectric layer, a floating gate, a control gate structure, and an erase gate structure. The stacked structure is disposed on the substrate, and includes a gate dielectric layer, an assist gate, and an insulation layer stacked in order. The tunneling dielectric layer is disposed on the substrate at one side of the stacked structure. The floating gate is disposed on the tunneling dielectric layer and includes an uppermost edge and a curved sidewall. The control gate structure covers the curved sidewall of the floating gate. The erase gate structure covers the floating gate and the control gate structure, and the uppermost edge of the floating gate is embedded in the erase gate structure.

公开(公告)号：US11991878B2

公开(公告)日：2024-05-21

申请号：US18133693

申请日：2023-04-12

Applicant: SK keyfoundry Inc.

Inventor： Kwang Il Kim ,  Yang Beom Kang ,  Jung Hwan Lee ,  Min Kuck Cho ,  Hyun Chul Kim

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/788 ,  H10B41/10 ,  H10B41/43 ,  H10B41/44

CPC classification number: H10B41/43 ,  H01L29/66825 ,  H01L29/788 ,  H10B41/10 ,  H10B41/44

Abstract: A semiconductor device include a nonvolatile memory device, including a first well region formed in a substrate, a tunneling gate insulator formed on the first well region, a floating gate formed on the tunneling gate insulator, a control gate insulator formed on the substrate, a control gate formed on the control gate insulator, and a first source region and a first drain region formed on opposite sides of the control gate, respectively, and a first logic device, including a first logic well region formed in the substrate, a first logic gate insulator formed on the first logic well region, a first logic gate formed on the first logic gate insulator, wherein the first logic gate comprises substantially a same material as a material of the control gate of the nonvolatile memory device.

公开(公告)号：US11856769B2

公开(公告)日：2023-12-26

申请号：US17531873

申请日：2021-11-22

Applicant: KEY FOUNDRY CO., LTD.

Inventor： Su Jin Kim

IPC: H10B41/60 ,  H10B41/44 ,  H10B41/47 ,  H10B41/48

CPC classification number: H10B41/60 ,  H10B41/44 ,  H10B41/47 ,  H10B41/48

Abstract: A semiconductor device includes a single poly non-volatile memory device including a sensing and selection gate structure, an erase gate structure, and a control gate structure. The sensing and selection gate structure includes a sensing gate and a selection gate, a bit line, a word line disposed on the selection gate, and a tunneling gate line. The erase gate structure includes an erase gate, and an erase gate line disposed near the erase gate. The control gate structure includes a control gate disposed on the substrate, and a control gate line disposed near the control gate. The sensing gate, the selection gate, the erase gate and the control gate are connected by one conductive layer. The erase gate structure implements a PMOS capacitor, an NMOS transistor, or a PMOS transistor. The semiconductor device includes a single poly non-volatile memory device including a separate program area and erase area.

公开(公告)号：US11758721B2

公开(公告)日：2023-09-12

申请号：US17202193

申请日：2021-03-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei Cheng Wu ,  Li-Feng Teng

IPC: H10B41/42 ,  H01L29/66 ,  H01L21/28 ,  H10B41/00 ,  H10B41/20 ,  H10B41/30 ,  H10B41/40 ,  H10B41/44 ,  H10B41/46 ,  H10B41/50 ,  H10B69/00 ,  H01L29/423

CPC classification number: H10B41/42 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/66825 ,  H10B41/00 ,  H10B41/20 ,  H10B41/30 ,  H10B41/40 ,  H10B41/44 ,  H10B41/46 ,  H10B41/50 ,  H10B69/00

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate. A second dielectric layer is disposed between the floating gate and the control gate, having one of a silicon nitride layer, a silicon oxide layer and multilayers thereof. A third dielectric layer is disposed between the second dielectric layer and the control gate, and includes a dielectric material having a dielectric constant higher than silicon nitride.