公开(公告)号：US11257922B2

公开(公告)日：2022-02-22

申请号：US16374162

申请日：2019-04-03

申请人： Winbond Electronics Corp.

发明人： Sih-Han Chen ,  Chien-Ting Chen ,  Yao-Ting Tsai ,  Hsiu-Han Liao

IPC分类号： H01L29/66 ,  H01L29/45 ,  H01L21/285

摘要： A method for forming a self-aligned contact includes providing a substrate with a plurality of gate structures formed on the substrate. The method also includes forming a spacer liner on the gate structures and the substrate. The method also includes forming a sacrificial layer between the gate structures and on the gate structures. The method also includes forming a plurality of dielectric plugs through the sacrificial layer above the gate structures. The method also includes removing the sacrificial layer to form a plurality of contact openings between the gate structures. The method also includes forming an etch resistant layer conformally covering the sidewall and the bottom of the contact openings. The method also includes forming a plurality of contact plugs in the contact openings.

公开(公告)号：US20200343256A1

公开(公告)日：2020-10-29

申请号：US16391326

申请日：2019-04-23

申请人： Winbond Electronics Corp.

发明人： Yao-Ting Tsai ,  Che-Fu Chuang ,  Jung-Ho Chang ,  Hsiu-Han Liao

IPC分类号： H01L27/11531 ,  H01L27/11521 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/49 ,  H01L29/45 ,  H01L29/78 ,  H01L29/788

摘要： Provided is an integrated circuit including a substrate, a plurality of first gate structures, a protective layer, a second gate structure, a source region, and a drain region. The substrate has a cell region and a peripheral region. The plurality of first gate structures are disposed in the cell region. A top surface and a sidewall of the plurality of first gate structures are covered by the protective layer. The second gate structure is disposed in the peripheral region. The source region and the drain region are disposed on the both side of the second gate structure. A manufacturing method of the integrated circuit is also provided.

公开(公告)号：US20180204846A1

公开(公告)日：2018-07-19

申请号：US15922888

申请日：2018-03-15

申请人： Winbond Electronics Corp.

发明人： Che-Fu Chuang ,  Hsiu-Han Liao ,  Yao-Ting Tsai

IPC分类号： H01L27/11521 ,  H01L29/417

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/41758 ,  H01L29/42328 ,  H01L29/4975 ,  H01L29/66825 ,  H01L29/7883

摘要： Provided is a memory device including a substrate, a source region, a drain region, a source contact, a drain contact, at least two stack gates, and at least two selection gates. The source region and the drain region are both located in the substrate. The source contact is located on the source region and the drain contact is located on the drain region. A bottom area of the drain contact is greater than a bottom area of the source contact. The stack gates are located on the substrate at two sides of the source region respectively. The selection gates are located on the substrate at two sides of the drain region respectively. A distance between the selection gates located at two sides of the drain region is greater than a distance between the stack gates located at two sides of the source region.

公开(公告)号：US20180047737A1

公开(公告)日：2018-02-15

申请号：US15352594

申请日：2016-11-16

申请人： Winbond Electronics Corp.

发明人： Che-Fu Chuang ,  Hsiu-Han Liao ,  Yao-Ting Tsai

IPC分类号： H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L21/28 ,  H01L29/788 ,  H01L29/49

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/41758 ,  H01L29/42328 ,  H01L29/4975 ,  H01L29/66825 ,  H01L29/7883

摘要： Provided is a memory device including a substrate and a gate structure. The gate structure is located on the substrate. The gate structure includes a stack gate and a selection gate aside the stack structure. A topmost surface of the selection gate is lower than a topmost surface of the stack gate.

公开(公告)号：US20150287914A1

公开(公告)日：2015-10-08

申请号：US14481925

申请日：2014-09-10

申请人： Winbond Electronics Corp.

发明人： Chia-Hua Ho ,  Shuo-Che Chang ,  Hsiu-Han Liao ,  Po-Yen Hsu ,  Meng-Hung Lin ,  Bo-Lun Wu ,  Ting-Ying Shen

IPC分类号： H01L45/00

CPC分类号： H01L45/1253 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16

摘要： Provided is a resistive random access memory including a first electrode layer, a second electrode layer, and a variable resistance layer disposed between the first electrode layer and the second electrode layer, wherein the second electrode layer includes a first sublayer, a second sublayer, and a conductive metal oxynitride layer disposed between the first sublayer and the second sublayer.

摘要翻译： 本发明提供一种电阻随机存取存储器，包括第一电极层，第二电极层和设置在第一电极层和第二电极层之间的可变电阻层，其中第二电极层包括第一子层，第二子层和 设置在第一子层和第二子层之间的导电金属氮氧化物层。

公开(公告)号：US20240244838A1

公开(公告)日：2024-07-18

申请号：US18617590

申请日：2024-03-26

申请人： Winbond Electronics Corp.

发明人： Che-Fu Chuang ,  Yao-Ting Tsai ,  Hsiu-Han Liao

IPC分类号： H10B41/30 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/788

CPC分类号： H10B41/30 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/66825 ,  H01L29/7883

摘要： Provided are a memory device and a method of manufacturing the same. The memory device includes: a stack structure; a first source/drain region and a second source/drain region located in a substrate beside the stack structure; a first self-aligned contact connected to the first source/drain region; a second self-aligned contact connected to the second source/drain region; a first liner structure located between the first self-aligned contact and a first sidewall of the stack structure; and a second liner structure located between the second self-aligned contact and a second sidewall of the stack structure. The first liner structure and the second liner structure are not connected and do not cover the stack structure.

公开(公告)号：US20220367496A1

公开(公告)日：2022-11-17

申请号：US17317872

申请日：2021-05-11

申请人： Winbond Electronics Corp.

发明人： Che-Fu Chuang ,  Hsiu-Han Liao

IPC分类号： H01L27/11526

摘要： A method for fabricating a semiconductor device includes: forming a first gate dielectric layer in a first and a second regions of a peripheral region of a substrate; forming a first conductive layer and a first hard mask layer over the substrate; forming a first mask layer on the first hard mask layer in the first region; removing the first hard mask layer outside the first region; removing the first hard mask layer; performing a wet etch process by taking the first hard mask layer as a mask, and removing the first conductive layer and the first gate dielectric layer outside the first region; removing the first hard mask layer and the first conductive layer; forming a second gate dielectric layer in the second region; and forming a first and a second gate conductive layers in the first and the second regions respectively.

公开(公告)号：US20220123007A1

公开(公告)日：2022-04-21

申请号：US17567850

申请日：2022-01-03

申请人： Winbond Electronics Corp.

发明人： Jian-Ting Chen ,  Yao-Ting Tsai ,  Hsiu-Han Liao

IPC分类号： H01L27/11556 ,  H01L29/788 ,  H01L29/66 ,  H01L21/8234

摘要： Provided is a manufacturing method of a memory device, including: forming a stacked layer on a substrate; patterning the stacked layer to form a plurality of openings in the stacked layer; forming a spacer on a sidewall of the openings; performing a first etching process by using the spacer as a mask to form a plurality of stack structures, wherein the spacer is embedded in the stack structures, such that a width of an upper portion of the stack structures is less than a width of a lower portion thereof; forming a dielectric layer on the stack structures and the spacer; and respectively forming a plurality of contact plugs on the substrate between the stack structures.

公开(公告)号：US11257833B2

公开(公告)日：2022-02-22

申请号：US16568297

申请日：2019-09-12

申请人： Winbond Electronics Corp.

发明人： Jian-Ting Chen ,  Yao-Ting Tsai ,  Hsiu-Han Liao

IPC分类号： H01L29/423 ,  H01L27/11556 ,  H01L29/788 ,  H01L29/66 ,  H01L21/8234

摘要： Provided is a memory device including a substrate, a plurality of stack structures, a spacer, a dielectric layer, and a plurality of contact plugs. The stack structures are disposed on the substrate. The spacer is embedded in the stack structures, so that a width of an upper portion of the stack structures is less than a width of a lower portion thereof. The dielectric layer conformally covers the stack structures and the spacer. The contact plugs are respectively disposed on the substrate between the stack structures.

公开(公告)号：US20220037345A1

公开(公告)日：2022-02-03

申请号：US17376079

申请日：2021-07-14

申请人： Winbond Electronics Corp.

发明人： Yao-Ting Tsai ,  Hsiu-Han Liao ,  Che-Fu Chuang

IPC分类号： H01L27/11531 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/66

摘要： Disposed are a semiconductor structure, a manufacturing method thereof and a flash memory. The semiconductor structure includes a substrate, first isolation structures, a gate structure and an oxide layer. The first isolation structures define a first active area in a peripheral region of the substrate. The oxide layer is disposed on the substrate in the first active area and covered by the first isolation structures. The oxide layer and the first isolation structures define an opening exposing the substrate. The gate structure is disposed on the substrate in the first active area and includes a gate dielectric layer disposed in the opening and a gate disposed on the gate dielectric layer. The oxide layer is located around the gate dielectric layer. The width of the bottom surface of the gate is less than that of the top surface of the first active area.