-
公开(公告)号：US09859291B2
公开(公告)日：2018-01-02
申请号：US14817187
申请日：2015-08-03
发明人： Tzung-Wen Cheng , Yu-Ming Cheng
IPC分类号： H01L27/115 , H01L27/11524
CPC分类号： H01L27/11524 , H01L27/11582 , H01L28/00
摘要： A non-volatile memory having memory cells is provided. A stacked gate structure has gate dielectric layer, assist gate, insulation layer, and erase gate disposed in order. The floating gate is disposed on a first sidewall of the stacked gate structure, the floating gate has a corner portion at the top portion, and erase gate covers the corner portion. The tunneling dielectric layer is disposed under the floating gate. The erase gate dielectric layer is disposed between the erase gate and the floating gate. The assist gate dielectric layer is disposed between the assist gate and the floating gate. The source region and the drain region are respectively disposed at two sides of the stacked structure and the floating gate. The control gate is disposed on the source region and the floating gate. The inter-gate dielectric layer is disposed between the control gate and the floating gate.
-
公开(公告)号：US20240274682A1
公开(公告)日：2024-08-15
申请号：US18108676
申请日：2023-02-13
发明人： Der-Tsyr Fan , I-Hsin Huang , Tzung-Wen Cheng , Yu-Ming Cheng
IPC分类号： H01L29/423 , H01L21/28 , H01L29/66 , H01L29/788 , H10B41/35
CPC分类号： H01L29/42328 , H01L29/40114 , H01L29/66825 , H01L29/7883 , H10B41/35
摘要： A non-volatile memory device includes at least one memory cell including a substrate, an assist gate, a byte select gate, a floating gate, and an upper gate. The substrate includes a first doped region and a second doped region. The assist gate is disposed on the substrate and adjacent to the second doped region. The byte select gate is disposed on the substrate and adjacent to the first doped region. The floating gate is disposed on the substrate and between the assist gate and byte select gate, and the floating gate includes an upper edge higher than top surfaces of the assist gate and the byte select gate. The upper gate covers the assist gate and the floating gate, and the upper gate is spaced apart from the byte select gate. The upper edge of the floating gate is embedded in the upper gate.
-
公开(公告)号：US20240162315A1
公开(公告)日：2024-05-16
申请号：US18090468
申请日：2022-12-28
发明人： Der-Tsyr Fan , I-Hsin Huang , Tzung-Wen Cheng , Yu-Ming Cheng
IPC分类号： H01L29/423 , H01L21/28 , H01L29/66 , H01L29/788 , H10B41/30
CPC分类号： H01L29/42328 , H01L29/40114 , H01L29/66825 , H01L29/7883 , H10B41/30
摘要： A non-volatile memory device includes at least one memory cell, and the memory cell includes a substrate, an assist gate structure, a tunneling dielectric layer, a floating gate, and an upper gate structure. The assist gate structure is disposed on the substrate. The floating gate includes two opposite first top edges arranged along a first direction, two opposite first sidewalls arranged along the first direction, and two opposite second sidewalls arranged along a second direction different from the first direction. The upper gate structure covers the assist gate structure and the floating gate, where at least one of the first top edges of the floating gate is embedded in the upper gate structure. Portions of the upper gate structure extend beyond the second sidewalls of the floating gate in the second direction, and the portions of the upper gate structure are disposed above the substrate.
-
公开(公告)号：US20230320088A1
公开(公告)日：2023-10-05
申请号：US17709370
申请日：2022-03-30
发明人： Der-Tsyr Fan , I-Hsin Huang , Tzung-Wen Cheng
IPC分类号： H01L27/11536 , H01L27/11543 , H01L27/11519
CPC分类号： H01L27/11536 , H01L27/11543 , H01L27/11519
摘要： A non-volatile memory device includes at least one memory cell, and the at least one memory cell includes a substrate, a stacked structure, a tunneling dielectric layer, a floating gate, a control gate structure, and an erase gate structure. The stacked structure is disposed on the substrate, and includes a gate dielectric layer, an assist gate, and an insulation layer stacked in order. The tunneling dielectric layer is disposed on the substrate at one side of the stacked structure. The floating gate is disposed on the tunneling dielectric layer and includes an uppermost edge and a curved sidewall. The control gate structure covers the curved sidewall of the floating gate. The erase gate structure covers the floating gate and the control gate structure, and the uppermost edge of the floating gate is embedded in the erase gate structure.
-
公开(公告)号：US20170040334A1
公开(公告)日：2017-02-09
申请号：US14817187
申请日：2015-08-03
发明人： Tzung-Wen Cheng , Yu-Ming Cheng
IPC分类号： H01L27/115
CPC分类号： H01L27/11524 , H01L27/11582 , H01L28/00
摘要： A non-volatile memory having memory cells is provided. A stacked gate structure has gate dielectric layer, assist gate, insulation layer, and erase gate disposed in order. The floating gate is disposed on a first sidewall of the stacked gate structure, the floating gate has a corner portion at the top portion, and erase gate covers the corner portion. The tunneling dielectric layer is disposed under the floating gate. The erase gate dielectric layer is disposed between the erase gate and the floating gate. The assist gate dielectric layer is disposed between the assist gate and the floating gate. The source region and the drain region are respectively disposed at two sides of the stacked structure and the floating gate. The control gate is disposed on the source region and the floating gate. The inter-gate dielectric layer is disposed between the control gate and the floating gate.
摘要翻译： 提供了具有存储单元的非易失性存储器。 堆叠栅极结构具有依次布置的栅极介电层，辅助栅极，绝缘层和擦除栅极。 浮置栅极设置在层叠栅极结构的第一侧壁上，浮动栅极在顶部具有角部，擦除栅极覆盖角部。 隧道电介质层设置在浮动栅极之下。 擦除栅介质层设置在擦除栅极和浮栅之间。 辅助栅极电介质层设置在辅助栅极和浮动栅极之间。 源极区域和漏极区域分别设置在堆叠结构和浮动栅极的两侧。 控制栅极设置在源极区域和浮动栅极上。 栅极间介电层设置在控制栅极和浮置栅极之间。
-
公开(公告)号：US20240304692A1
公开(公告)日：2024-09-12
申请号：US18226788
申请日：2023-07-27
发明人： Der-Tsyr Fan , I-Hsin Huang , Tzung-Wen Cheng , Yu-Ming Cheng
IPC分类号： H01L29/423 , H10B41/30
CPC分类号： H01L29/42328 , H10B41/30
摘要： A non-volatile memory device includes at least one memory cell, and the memory cell includes a substrate, a select gate, a floating gate, a floating gate cap layer, and an erase gate. The select gate is disposed on the substrate. The floating gate is disposed on the substrate and laterally spaced apart from the select gate, where the floating gate includes top edges forming a closed shape as viewed from a top-down perspective. The floating gate cap layer is disposed on a top surface of the floating gate, where an area of a top surface of the floating gate cap layer is less than an area of a bottom surface of the floating gate. The erase gate is disposed on the floating gate, and one or more of the top edges are covered with the erase gate. A control gate is covered with the erase gate.
-
公开(公告)号：US20240162317A1
公开(公告)日：2024-05-16
申请号：US18382069
申请日：2023-10-20
发明人： Der-Tsyr Fan , I-Hsin Huang , Tzung-Wen Cheng , Yu-Ming Cheng , Chen-Ming Tsai
IPC分类号： H01L29/423 , H01L21/28 , H01L29/66 , H01L29/788 , H10B41/30
CPC分类号： H01L29/42328 , H01L29/40114 , H01L29/66825 , H01L29/7883 , H10B41/30
摘要： A non-volatile memory device includes a memory cell including a substrate, a select gate, a control gate, a planar floating gate, a coupling dielectric layer, an erase gate dielectric layer, and an erase gate. The select gate and the control gate are disposed on the substrate and laterally spaced apart from each other, and the control gate includes a non-vertical surface. The planar floating gate includes a lateral tip laterally spaced apart from the control gate. The coupling dielectric layer includes a first thickness (T1). The erase gate dielectric layer covers the non-vertical surface of the control gate and the lateral tip of the planar floating gate, and includes a second thickness (T2). The erase gate covers the erase gate dielectric layer and the lateral tip of the planar floating gate. The first thickness and the second thickness satisfy the following relation: (T2)
-
公开(公告)号：US20240162316A1
公开(公告)日：2024-05-16
申请号：US18377319
申请日：2023-10-06
发明人： Der-Tsyr Fan , I-Hsin Huang , Tzung-Wen Cheng , Yu-Ming Cheng
IPC分类号： H01L29/423 , H01L21/28 , H01L29/66 , H01L29/788 , H10B41/30
CPC分类号： H01L29/42328 , H01L29/40114 , H01L29/66825 , H01L29/7883 , H10B41/30
摘要： A non-volatile memory device includes at least one memory cell and the memory cell includes a substrate, a select gate, a control gate, a floating gate, and an erase gate. The select gate is disposed on the substrate, and the control gate is disposed on the substrate and laterally spaced apart from the select gate. The control gate comprises a non-vertical surface. The floating gate includes a vertical portion and a horizontal portion. The vertical portion disposed between the select gate and the control gate and includes a first top tip laterally spaced apart from the control gate. The horizontal portion is disposed between the substrate and the control gate, where the horizontal portion includes a lateral tip laterally and vertically spaced apart from the control gate. The erase gate covers the non-vertical surface of the control gate and the lateral tip of the horizontal portion of the floating gate.
-
-
-
-
-
-
-
搜索结果
8 条记录 (耗时 0.012 秒)
