公开(公告)号：US20230320088A1

公开(公告)日：2023-10-05

申请号：US17709370

申请日：2022-03-30

申请人： IOTMEMORY TECHNOLOGY INC.

发明人： Der-Tsyr Fan ,  I-Hsin Huang ,  Tzung-Wen Cheng

IPC分类号： H01L27/11536 ,  H01L27/11543 ,  H01L27/11519

CPC分类号： H01L27/11536 ,  H01L27/11543 ,  H01L27/11519

摘要： A non-volatile memory device includes at least one memory cell, and the at least one memory cell includes a substrate, a stacked structure, a tunneling dielectric layer, a floating gate, a control gate structure, and an erase gate structure. The stacked structure is disposed on the substrate, and includes a gate dielectric layer, an assist gate, and an insulation layer stacked in order. The tunneling dielectric layer is disposed on the substrate at one side of the stacked structure. The floating gate is disposed on the tunneling dielectric layer and includes an uppermost edge and a curved sidewall. The control gate structure covers the curved sidewall of the floating gate. The erase gate structure covers the floating gate and the control gate structure, and the uppermost edge of the floating gate is embedded in the erase gate structure.

公开(公告)号：US20220359551A1

公开(公告)日：2022-11-10

申请号：US17872534

申请日：2022-07-25

申请人： Shanghai Huali Integrated Circuit Corporation

发明人： Zhi Tian ,  Juanjuan Li ,  Hua Shao ,  Haoyu Chen

IPC分类号： H01L27/11536 ,  H01L27/06 ,  H01L27/11539 ,  H01L49/02 ,  H01L29/66 ,  H01L29/788

摘要： The present disclosure provides a stack capacitor, a flash memory device, and a manufacturing method thereof. The stack capacitor of the flash memory device has a a memory transistor structure which at least comprises a substrate, and a tunneling oxide layer, a floating gate layer, an interlayer dielectric layer and a control gate layer which are sequentially stacked on the substrate, the interlayer dielectric layer of the stack capacitor comprises a first oxide layer and a nitride layer; the stack capacitor further comprises a first contact leading out of the control gate layer and a second contact leading out of the floating gate layer. The capacitance per unit area of the stack capacitor provided by the disclosure is effectively improved, and the size of the transistor device is reduced. The manufacturing method according to the disclosure does not add any additional photomask than a conventional process flow.

公开(公告)号：US11437387B2

公开(公告)日：2022-09-06

申请号：US17213885

申请日：2021-03-26

申请人： SHANGHAI HUALI MICROELECTRONICS CORPORATION

发明人： Zhi Tian ,  Juanjuan Li ,  Hua Shao ,  Haoyu Chen

IPC分类号： H01L21/00 ,  H01L27/11536 ,  H01L27/06 ,  H01L27/11539 ,  H01L49/02 ,  H01L29/66 ,  H01L29/788

摘要： The present disclosure provides a stack capacitor, a flash memory device, and a manufacturing method thereof. The stack capacitor of the flash memory device has a a memory transistor structure which at least comprises a substrate, and a tunneling oxide layer, a floating gate layer, an interlayer dielectric layer and a control gate layer which are sequentially stacked on the substrate, the interlayer dielectric layer of the stack capacitor comprises a first oxide layer and a nitride layer; the stack capacitor further comprises a first contact leading out of the control gate layer and a second contact leading out of the floating gate layer. The capacitance per unit area of the stack capacitor provided by the disclosure is effectively improved, and the size of the transistor device is reduced. The manufacturing method according to the disclosure does not add any additional photomask than a conventional process flow.

公开(公告)号：US11289498B2

公开(公告)日：2022-03-29

申请号：US16801266

申请日：2020-02-26

申请人： KEY FOUNDRY CO., LTD.

发明人： Kwang Il Kim ,  Yang Beom Kang ,  Jung Hwan Lee ,  Min Kuck Cho ,  Hyun Chul Kim

IPC分类号： H01L21/00 ,  H01L27/11534 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11519 ,  H01L27/11536

摘要： A semiconductor device include a nonvolatile memory device, including a first well region formed in a substrate, a tunneling gate insulator formed on the first well region, a floating gate formed on the tunneling gate insulator, a control gate insulator formed on the substrate, a control gate formed on the control gate insulator, and a first source region and a first drain region formed on opposite sides of the control gate, respectively, and a first logic device, including a first logic well region formed in the substrate, a first logic gate insulator formed on the first logic well region, a first logic gate formed on the first logic gate insulator, wherein the first logic gate comprises substantially a same material as a material of the control gate of the nonvolatile memory device.

公开(公告)号：US10833179B2

公开(公告)日：2020-11-10

申请号：US16576389

申请日：2019-09-19

申请人： Silicon Storage Technology, Inc.

发明人： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC分类号： H01L27/11521 ,  H01L27/11531 ,  H01L29/66 ,  H01L21/3213 ,  H01L27/11536 ,  H01L29/423 ,  H01L49/02

摘要： A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

公开(公告)号：US10720439B2

公开(公告)日：2020-07-21

申请号：US15404005

申请日：2017-01-11

申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION ,  SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION

发明人： Changgeng Song

IPC分类号： H01L27/11573 ,  H01L27/11543 ,  H01L21/28 ,  H01L21/764 ,  H01L27/11539 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11524 ,  H01L27/11541 ,  H01L29/423 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/06 ,  H01L29/49 ,  H01L27/1157

摘要： A method for manufacturing a semiconductor device includes providing a substrate structure having an active region, a gate insulating layer, a charge storage layer, a gate dielectric layer, and a gate layer sequentially formed on the active region. The method also includes forming a patterned metal layer on the substrate structure, removing a respective portion of the gate layer, the gate dielectric layer, the charge storage layer using the patterned metal gate layer as a mask to form multiple gate structures separated from each other by a space. The gate structures each include a stack containing a second portion of the charge storage layer, the gate dielectric layer, the gate layer, and one of the gate lines. The method further includes forming an interlayer dielectric layer on a surface of the gate structures stretching over the space while forming an air gap in the space.

公开(公告)号：US10580785B2

公开(公告)日：2020-03-03

申请号：US15916241

申请日：2018-03-08

申请人： Renesas Electronics Corporation

发明人： Shibun Tsuda

IPC分类号： H01L29/78 ,  H01L27/11573 ,  H01L27/1157 ,  H01L21/762 ,  H01L29/792 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11536 ,  H01L29/49

摘要： A semiconductor device of the present invention includes: an element isolation part which is disposed between fins and whose height is lower than the height of each fin; a memory gate electrode placed over the fins and the element isolation part with a memory gate insulating film having a charge storage part in between; and a control gate electrode disposed in line with the memory gate electrode. The height of the element isolation part below the memory gate electrode is higher than the height of the element isolation part below the control gate electrode. A mismatch between electron injection and hole injection is improved, rewriting operation speed is accelerated, and reliability is enhanced by making the height of the element isolation part below the memory gate electrode higher than the height of the element isolation part below the control gate electrode as mentioned above.

公开(公告)号：US20200013882A1

公开(公告)日：2020-01-09

申请号：US16576348

申请日：2019-09-19

申请人： Silicon Storage Technology, Inc.

发明人： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC分类号： H01L29/66 ,  H01L21/3213 ,  H01L27/11521 ,  H01L27/11536 ,  H01L27/11531 ,  H01L29/423 ,  H01L49/02

摘要： A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

公开(公告)号：US10147733B2

公开(公告)日：2018-12-04

申请号：US15364603

申请日：2016-11-30

申请人： STMicroelectronics (Rousset) SAS

发明人： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC分类号： H01L29/66 ,  H01L27/11531 ,  H01L29/739 ,  H01L27/08 ,  H01L27/11526 ,  G11C16/04 ,  H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/861 ,  H01L29/16 ,  H01L27/06 ,  H01L27/12 ,  H01L29/36 ,  H01L27/11536

摘要： A method can be used to make a semiconductor device. A number of projecting regions are formed over a first semiconductor layer that has a first conductivity type. The first semiconductor layer is located on an insulating layer that overlies a semiconductor substrate. The projecting regions are spaced apart from each other. Using the projecting regions as an implantation mask, dopants having a second conductivity type are implanted into the first semiconductor layer, so as to form a sequence of PN junctions forming diodes in the first semiconductor layer. The diodes vertically extend from an upper surface of the first semiconductor layer to the insulating layer.

公开(公告)号：US09721958B2

公开(公告)日：2017-08-01

申请号：US15003659

申请日：2016-01-21

申请人： Silicon Storage Technology, Inc.

发明人： Jeng-Wei Yang ,  Chun-Ming Chen ,  Man-Tang Wu ,  Feng Zhou ,  Xian Liu ,  Chien-Sheng Su ,  Nhan Do

IPC分类号： H01L21/336 ,  H01L27/11524 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11536 ,  H01L21/306

CPC分类号： H01L27/11524 ,  H01L21/28273 ,  H01L21/30604 ,  H01L27/11536 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

摘要： A method of forming a memory device by forming spaced apart first and second regions with a channel region therebetween, forming a floating gate over and insulated from a first portion of the channel region, forming a control gate over and insulated from the floating gate, forming an erase gate over and insulated from the first region, and forming a select gate over and insulated from a second portion of the channel region. Forming of the floating gate includes forming a first insulation layer on the substrate, forming a first conductive layer on the first insulation layer, and performing two separate etches to form first and second trenches through the first conductive layer. A sidewall of the first conductive layer at the first trench has a negative slope and a sidewall of the first conductive layer at the second trench is vertical.