公开(公告)号：US20210305423A1

公开(公告)日：2021-09-30

申请号：US16943993

申请日：2020-07-30

申请人： SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION

发明人： Zhi Tian ,  Juanjuan Li ,  Hua Shao ,  Haoyu Chen

IPC分类号： H01L29/788 ,  H01L29/78 ,  H01L27/088

摘要： The present disclosure provides a device structure for increasing the coupling ratio of a body-tied fin flash memory cell. The device includes a plurality of elongate fin structures arranged in parallel in an active layer on a substrate, a floating gate disposed on the top surface and the opposing sidewalls of each of the fin structures and at a predetermined location on the elongated fin, and dispersed structure. The dispersed structure comprises a plurality of stacked layers parallel to the substrate, spaced evenly apart; and two adjacent fin structures share one dispersed structure at their sidewalls. This device increases the distance between adjacent floating gates, reduces coupling capacitance, and reduces the disturbance between the cells, which is conducive to increasing the drain voltage, improving the programming speed, and further reducing the gate voltage. More optimization options for subsequent shrinking of the flash memory cells can be provided.

公开(公告)号：US20230065976A1

公开(公告)日：2023-03-02

申请号：US17880280

申请日：2022-08-03

申请人： Shanghai Huali Integrated Circuit Corporation

发明人： Linghao Xiong ,  Feng Ji ,  Haoyu Chen ,  Qiwei Wang

IPC分类号： H01L27/146

摘要： An isolation trench structure for a backside illuminated CMOS image sensor is disclosed. Each pixel cell in the backside illuminated CMOS image sensor comprises a photodiode and a cell isolation trench structure. A first cell trench combination structure containing more than five first cell trenches is formed in each active area, the cell isolation trench structure is formed in the first cell trench of the first cell trench combination structure, and the first cell trench extends longitudinally through an N-type area of the photodiode or is located in the N-type area of the photodiode. In a plan view, first ends of all the first cell trenches converge toward the center of the active area, and second ends of all the first cell trenches diverge from each other toward the edge of the active area, so as to divide the active area into a plurality of active area subblocks.

公开(公告)号：US20230091032A1

公开(公告)日：2023-03-23

申请号：US17899402

申请日：2022-08-30

申请人： Shanghai Huali Integrated Circuit Corporation

发明人： Xiang Peng ,  Haoyu Chen ,  Feng Ji

IPC分类号： H01L27/146

摘要： The present application provides a backside illuminated CMOS image sensor and a method of making the same. The backside illuminated CMOS image sensor comprises: a pixel region substrate, an isolation structure, a first dielectric layer, a metal grid, and second dielectric layer, wherein grid trenches and a metal plug are formed in the pixel region substrate, the isolation structure is located in each of the grid trenches and on the surface of the pixel region substrate outside of the grid trenches, and the isolation structure comprises a high-K dielectric layer, an insulating layer, and a metal core layer.

公开(公告)号：US11315969B2

公开(公告)日：2022-04-26

申请号：US16943468

申请日：2020-07-30

申请人： SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION

发明人： Zhi Tian ,  Juanjuan Li ,  Hua Shao ,  Haoyu Chen

IPC分类号： H01L27/146

摘要： The present application provides a buried tri-gate fin vertical gate structure. Which includes a transfer transistor on an epitaxial layer; a photodiode in the epitaxial layer at one side of the transfer transistor. A reset transistor on the epi-layer includes N+ regions at both sides of its gate, one of the N+ regions forms a floating diffusion node. The bottom of the fin vertical gate protrudes into the epitaxial layer with a number of vertical portions. Thus, increased surface areas enhance charge motion at the bottom, combining large-area transfer at an upper layer by the vertical gate and quick transfer at the bottom by the FINFET, thereby improving photo response.

公开(公告)号：US20210305297A1

公开(公告)日：2021-09-30

申请号：US16943468

申请日：2020-07-30

申请人： SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION

发明人： Zhi Tian ,  Juanjuan Li ,  Hua Shao ,  Haoyu Chen

IPC分类号： H01L27/146

摘要： The present application provides a buried tri-gate fin vertical gate structure. Which includes a transfer transistor on an epitaxial layer; a photodiode in the epitaxial layer at one side of the transfer transistor. A reset transistor on the epi-layer includes N+ regions at both sides of its gate, one of the N+ regions forms a floating diffusion node. The bottom of the fin vertical gate protrudes into the epitaxial layer with a number of vertical portions. Thus, increased surface areas enhance charge motion at the bottom, combining large-area transfer at an upper layer by the vertical gate and quick transfer at the bottom by the FINFET, thereby improving photo response.

公开(公告)号：US11737268B2

公开(公告)日：2023-08-22

申请号：US17872534

申请日：2022-07-25

申请人： Shanghai Huali Integrated Circuit Corporation

发明人： Zhi Tian ,  Juanjuan Li ,  Hua Shao ,  Haoyu Chen

IPC分类号： H01L21/00 ,  H10B41/44 ,  H01L27/06 ,  H01L49/02 ,  H01L29/66 ,  H01L29/788 ,  H10B41/46

CPC分类号： H10B41/44 ,  H01L27/0629 ,  H01L28/40 ,  H01L29/66825 ,  H01L29/788 ,  H10B41/46

摘要： The present disclosure provides a stack capacitor, a flash memory device, and a manufacturing method thereof. The stack capacitor of the flash memory device has a a memory transistor structure which at least comprises a substrate, and a tunneling oxide layer, a floating gate layer, an interlayer dielectric layer and a control gate layer which are sequentially stacked on the substrate, the interlayer dielectric layer of the stack capacitor comprises a first oxide layer and a nitride layer; the stack capacitor further comprises a first contact leading out of the control gate layer and a second contact leading out of the floating gate layer. The capacitance per unit area of the stack capacitor provided by the disclosure is effectively improved, and the size of the transistor device is reduced. The manufacturing method according to the disclosure does not add any additional photomask than a conventional process flow.

公开(公告)号：US20230142968A1

公开(公告)日：2023-05-11

申请号：US17958583

申请日：2022-10-03

申请人： Shanghai Huali Integrated Circuit Corporation

发明人： Xiaoliang Tang ,  Haoyu Chen ,  Hua Shao

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L21/28123 ,  H01L21/28079 ,  H01L29/495 ,  H01L29/66545

摘要： The present application discloses a method for manufacturing a high-voltage metal gate device. After the deposition of a gate metal through a normal process, in CMP processes performed to the gate metal, firstly a first CMP process is performed to thin the gate metal to a certain thickness in advance, then a blocking dielectric layer is deposited, a large-area high-voltage gate region is opened through photolithography, and the blocking dielectric layer other than the blocking dielectric layer in the large-area high-voltage gate region is removed through etching. In a second CMP process performed to the gate metal, due to the blocking dielectric layer on the surface of the large-area gate metal in the high-voltage gate region, the polishing speed is slow, and CMP dishing will not be caused.

公开(公告)号：US20220359551A1

公开(公告)日：2022-11-10

申请号：US17872534

申请日：2022-07-25

申请人： Shanghai Huali Integrated Circuit Corporation

发明人： Zhi Tian ,  Juanjuan Li ,  Hua Shao ,  Haoyu Chen

IPC分类号： H01L27/11536 ,  H01L27/06 ,  H01L27/11539 ,  H01L49/02 ,  H01L29/66 ,  H01L29/788

摘要： The present disclosure provides a stack capacitor, a flash memory device, and a manufacturing method thereof. The stack capacitor of the flash memory device has a a memory transistor structure which at least comprises a substrate, and a tunneling oxide layer, a floating gate layer, an interlayer dielectric layer and a control gate layer which are sequentially stacked on the substrate, the interlayer dielectric layer of the stack capacitor comprises a first oxide layer and a nitride layer; the stack capacitor further comprises a first contact leading out of the control gate layer and a second contact leading out of the floating gate layer. The capacitance per unit area of the stack capacitor provided by the disclosure is effectively improved, and the size of the transistor device is reduced. The manufacturing method according to the disclosure does not add any additional photomask than a conventional process flow.

公开(公告)号：US11282968B2

公开(公告)日：2022-03-22

申请号：US16943993

申请日：2020-07-30

申请人： SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION

发明人： Zhi Tian ,  Juanjuan Li ,  Hua Shao ,  Haoyu Chen

IPC分类号： H01L29/788 ,  H01L27/088 ,  H01L29/78

摘要： The present disclosure provides a device structure for increasing the coupling ratio of a body-tied fin flash memory cell. The device includes a plurality of elongate fin structures arranged in parallel in an active layer on a substrate, a floating gate disposed on the top surface and the opposing sidewalls of each of the fin structures and at a predetermined location on the elongated fin, and dispersed structure. The dispersed structure comprises a plurality of stacked layers parallel to the substrate, spaced evenly apart; and two adjacent fin structures share one dispersed structure at their sidewalls. This device increases the distance between adjacent floating gates, reduces coupling capacitance, and reduces the disturbance between the cells, which is conducive to increasing the drain voltage, improving the programming speed, and further reducing the gate voltage. More optimization options for subsequent shrinking of the flash memory cells can be provided.