公开(公告)号：US12120881B2

公开(公告)日：2024-10-15

申请号：US16931500

申请日：2020-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongsoon Lim ,  Daeseok Byeon

IPC: H10B43/40 ,  G11C7/18 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/46 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/40 ,  G11C7/18 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/46 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Disclosed is a three-dimensional semiconductor device comprising channel regions that penetrate the stack structure and extend in a direction perpendicular to a top surface of the first substrate, a first interlayer dielectric layer on the stack structure, and a peripheral circuit structure on the first interlayer dielectric layer. The peripheral circuit structure includes peripheral circuit elements on a first surface of a second substrate. The peripheral circuit elements are electrically connected to the channel regions and at least one of the gate electrodes. The first substrate has a first crystal plane parallel to the top surface thereof. The second substrate has a second crystal plane parallel to the first surface thereof. An arrangement direction of atoms of the first crystal plane intersects an arrangement direction of atoms of the second crystal plane.

公开(公告)号：US20230240068A1

公开(公告)日：2023-07-27

申请号：US18194258

申请日：2023-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung Yang ,  Byungjin Lee ,  Bumkyu Kang ,  Dong-Sik Lee

IPC: H10B41/46 ,  H01L23/528 ,  H01L23/522 ,  G11C16/08 ,  G11C7/18 ,  H10B41/10 ,  H10B41/20 ,  H10B41/48 ,  H10B43/10 ,  H10B43/20 ,  H10B43/40

CPC classification number: H10B41/46 ,  G11C7/18 ,  G11C16/08 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/20 ,  H10B41/48 ,  H10B43/10 ,  H10B43/20 ,  H10B43/40

Abstract: A three-dimensional semiconductor memory device including a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, the first memory including a first stack structure having first electrode layers stacked on one another and first inter-electrode dielectric layers therebetween, a first planarized dielectric layer covering an end of the first stack structure, and a through via that penetrates the end of the first stack structure, the through via electrically connected to one of the decoder circuits, and a second memory on the first memory and including a second stack structure having second electrode layers stacked on one another and second inter-electrode dielectric layers therebetween, a second planarized dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through via.

公开(公告)号：US12069858B2

公开(公告)日：2024-08-20

申请号：US18194258

申请日：2023-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung Yang ,  Byungjin Lee ,  Bumkyu Kang ,  Dong-Sik Lee

IPC: H10B41/20 ,  G11C7/18 ,  G11C16/08 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/46 ,  H10B41/48 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B41/46 ,  G11C7/18 ,  G11C16/08 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/20 ,  H10B41/48 ,  H10B43/10 ,  H10B43/20 ,  H10B43/40

Abstract: A three-dimensional semiconductor memory device including a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, the first memory including a first stack structure having first electrode layers stacked on one another and first inter-electrode dielectric layers therebetween, a first planarized dielectric layer covering an end of the first stack structure, and a through via that penetrates the end of the first stack structure, the through via electrically connected to one of the decoder circuits, and a second memory on the first memory and including a second stack structure having second electrode layers stacked on one another and second inter-electrode dielectric layers therebetween, a second planarized dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through via.

公开(公告)号：US12016178B2

公开(公告)日：2024-06-18

申请号：US18097592

申请日：2023-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung-Hee Kim ,  Woo Choel Noh ,  Ik Soo Kim ,  Jun Kwan Kim ,  Jinsub Kim ,  Yongjin Shin

IPC: H10B41/46 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20 ,  H10B43/40

CPC classification number: H10B41/46 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20 ,  H10B43/40

Abstract: A semiconductor device including a substrate that includes a cell array region and a peripheral circuit region; a cell transistor on the cell array region of the substrate; a peripheral transistor on the peripheral circuit region of the substrate; a first interconnection layer connected to the cell transistor; a second interconnection layer connected to the peripheral transistor; an interlayer dielectric layer covering the first interconnection layer; and a blocking layer spaced apart from the first interconnection layer, the blocking layer covering a top surface and a sidewall of the second interconnection layer.

公开(公告)号：US11903193B2

公开(公告)日：2024-02-13

申请号：US17863749

申请日：2022-07-13

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Chi-Chung Jen ,  Yu-Chu Lin ,  Y. C. Kuo ,  Wen-Chih Chiang ,  Keng-Ying Liao ,  Huai-Jen Tung

IPC: H01L21/28 ,  H10B41/46 ,  H01L29/423 ,  H10B41/30 ,  H01L29/51

CPC classification number: H10B41/46 ,  H01L29/40114 ,  H01L29/42336 ,  H10B41/30 ,  H01L29/513

Abstract: A MOSFET device and method of making, the device including a floating gate layer formed within a trench in a substrate, a tunnel dielectric layer located on sidewalls and a bottom of the trench, a control gate dielectric layer located on a top surface of the floating gate layer, a control gate layer located on a top surface of the control gate dielectric layer and sidewall spacers located on sidewalls of the control gate dielectric layer and the control gate layer.

公开(公告)号：US11758721B2

公开(公告)日：2023-09-12

申请号：US17202193

申请日：2021-03-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei Cheng Wu ,  Li-Feng Teng

IPC: H10B41/42 ,  H01L29/66 ,  H01L21/28 ,  H10B41/00 ,  H10B41/20 ,  H10B41/30 ,  H10B41/40 ,  H10B41/44 ,  H10B41/46 ,  H10B41/50 ,  H10B69/00 ,  H01L29/423

CPC classification number: H10B41/42 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66545 ,  H01L29/66825 ,  H10B41/00 ,  H10B41/20 ,  H10B41/30 ,  H10B41/40 ,  H10B41/44 ,  H10B41/46 ,  H10B41/50 ,  H10B69/00

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate. A second dielectric layer is disposed between the floating gate and the control gate, having one of a silicon nitride layer, a silicon oxide layer and multilayers thereof. A third dielectric layer is disposed between the second dielectric layer and the control gate, and includes a dielectric material having a dielectric constant higher than silicon nitride.

公开(公告)号：US11737268B2

公开(公告)日：2023-08-22

申请号：US17872534

申请日：2022-07-25

Applicant: Shanghai Huali Integrated Circuit Corporation

Inventor： Zhi Tian ,  Juanjuan Li ,  Hua Shao ,  Haoyu Chen

IPC: H01L21/00 ,  H10B41/44 ,  H01L27/06 ,  H01L49/02 ,  H01L29/66 ,  H01L29/788 ,  H10B41/46

CPC classification number: H10B41/44 ,  H01L27/0629 ,  H01L28/40 ,  H01L29/66825 ,  H01L29/788 ,  H10B41/46

Abstract: The present disclosure provides a stack capacitor, a flash memory device, and a manufacturing method thereof. The stack capacitor of the flash memory device has a a memory transistor structure which at least comprises a substrate, and a tunneling oxide layer, a floating gate layer, an interlayer dielectric layer and a control gate layer which are sequentially stacked on the substrate, the interlayer dielectric layer of the stack capacitor comprises a first oxide layer and a nitride layer; the stack capacitor further comprises a first contact leading out of the control gate layer and a second contact leading out of the floating gate layer. The capacitance per unit area of the stack capacitor provided by the disclosure is effectively improved, and the size of the transistor device is reduced. The manufacturing method according to the disclosure does not add any additional photomask than a conventional process flow.

公开(公告)号：US12058855B2

公开(公告)日：2024-08-06

申请号：US18472879

申请日：2023-09-22

Applicant: SK hynix Inc.

Inventor： Sung Lae Oh

IPC: H10B41/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/46 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B41/27 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/46 ,  H10B43/10 ,  H10B43/27

Abstract: A method for manufacturing a three-dimensional memory device comprises: forming a first pre-stack by alternately stacking a plurality of first interlayer dielectric layers and a plurality of first sacrificial layers in a vertical direction; forming, in the first pre-stack, a first staircase part; forming a plurality of first vertical vias, which pass through the first staircase part, and a plurality of second vertical vias that pass through a first coupling part of the first pre-stack; forming a second pre-stack by alternately stacking a plurality of second interlayer dielectric layers and a plurality of second sacrificial layers on the first pre-stack; forming, in the second pre-stack, a second staircase part; forming a plurality of third vertical vias and a plurality of fourth vertical vias; and replacing the first and second sacrificial layers with an electrode material.

公开(公告)号：US12035523B2

公开(公告)日：2024-07-09

申请号：US17532675

申请日：2021-11-22

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Wenxiang Xu ,  Haohao Yang ,  Pan Huang ,  Ping Yan ,  Zongliang Huo ,  Wenbin Zhou ,  Wei Xu

IPC: H10B41/10 ,  H01L23/522 ,  H10B41/27 ,  H10B41/46 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B41/46 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: Embodiments of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a structure strengthen plug in an upper portion of the alternating dielectric stack, wherein the structure strengthen plug has a narrow support body and two enlarged connecting portions; forming a gate line silt in the alternating dielectric stack to expose a sidewall of one enlarged connecting portion of the structure strengthen plug; and forming a gate line slit structure in the gate line slit including an enlarged end portion connected to the one enlarged connecting portion of the structure strengthen plug.

公开(公告)号：US11943915B2

公开(公告)日：2024-03-26

申请号：US17170050

申请日：2021-02-08

Applicant: SK hynix Inc.

Inventor： Sung Lae Oh

IPC: H10B41/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/46 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B41/27 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/46 ,  H10B43/10 ,  H10B43/27

Abstract: A three-dimensional memory device includes a lower stack and an upper stack stacked one on the other, and each including a plurality of word lines which are stacked alternately with a plurality of interlayer dielectric layers, wherein each of the lower stack and the upper stack includes a first cell part, a second cell part, a coupling part which couples the first cell part and the second cell part, and a staircase part which extends parallel to the coupling part from the first cell part and in which pad areas of the word lines are disposed in a stepwise manner, and wherein the coupling part of the upper stack is disposed to overlap with the staircase part of the lower stack, and the staircase part of the upper stack is disposed to overlap with the coupling part of the lower stack.