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公开(公告)号：US20240155848A1
公开(公告)日：2024-05-09
申请号：US18414135
申请日：2024-01-16
发明人： Jin-Woo Han , Yuniarto Widjaja
摘要： A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) with increased on-state current obtained through a parasitic bipolar junction transistor (BJT) of the MOSFET. Methods of operating the MOSFET as a memory cell or a memory array select transistor are provided.
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公开(公告)号：US20230217663A1
公开(公告)日：2023-07-06
申请号：US18171497
申请日：2023-02-20
发明人： Jin-Woo Han , Yuniarto Widjaja
摘要： A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) with increased on-state current obtained through a parasitic bipolar junction transistor (BJT) of the MOSFET. Methods of operating the MOSFET as a memory cell or a memory array select transistor are provided.
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3.发明授权公开(公告)号：US12125786B2
公开(公告)日：2024-10-22
申请号：US17819004
申请日：2022-08-11
IPC分类号： H01L23/528 , H01L21/768 , H01L23/522 , H10B41/00 , H10B41/35 , H10B41/50 , H10B43/35 , H10B43/50
CPC分类号： H01L23/5283 , H01L21/76816 , H01L21/76877 , H01L23/5226 , H10B43/50 , H10B41/00 , H10B41/35 , H10B41/50 , H10B43/35
摘要： Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.
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4.发明公开公开(公告)号：US20230301076A1
公开(公告)日：2023-09-21
申请号：US18321487
申请日：2023-05-22
发明人： François Tailliet
IPC分类号： H10B41/00 , H01L29/423 , G11C7/18 , H01L29/66 , G11C16/04 , H01L21/28 , G11C16/08 , G11C16/24 , H10B41/35
CPC分类号： H10B41/00 , G11C7/18 , G11C16/0433 , G11C16/08 , G11C16/24 , H01L29/40114 , H01L29/42324 , H01L29/42328 , H01L29/42336 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66825 , H10B41/35 , H01L29/7881
摘要： An EEPROM memory integrated circuit includes memory cells arranged in a memory plane. Each memory cell includes an access transistor in series with a state transistor. Each access transistor is coupled, via its source region, to the corresponding source line and each state transistor is coupled, via its drain region, to the corresponding bit line. The floating gate of each state transistor rests on a dielectric layer having a first part with a first thickness, and a second part with a second thickness that is less than the first thickness. The second part is located on the source side of the state transistor.
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公开(公告)号：US12119336B2
公开(公告)日：2024-10-15
申请号：US17883682
申请日：2022-08-09
发明人： Hyunmog Park , Daehyun Kim , Jinmin Kim , Hei Seung Kim , Hyunsik Park , Sangkil Lee
IPC分类号： H01L25/18 , G11C14/00 , G11C16/04 , H01L23/48 , H01L23/522 , H01L25/00 , H10B41/00 , H10B41/27 , H10B43/27 , G11C13/00 , H10B41/41
CPC分类号： H01L25/18 , G11C14/0018 , G11C16/04 , H01L23/481 , H01L23/5226 , H01L25/50 , H10B41/27 , H10B43/27 , G11C13/0004 , H10B41/41
摘要： Disclosed are fusion memory devices and methods of fabricating the same. The fusion memory device comprises a first memory device including a first substrate having active and inactive surfaces opposite to each other and a first memory cell circuit on the active surface of the first substrate, a non-memory device including a second substrate having active and inactive surfaces opposite to each other and a non-memory circuit on the active surface of the second substrate, the non-memory device being provided on the first memory device, and a second memory device on the inactive surface of the second substrate and including a second memory cell circuit different from the first memory cell circuit. The non-memory device lies between the first and second memory cell circuits and controls an electrical operation of each of the first and second memory cell circuits.
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公开(公告)号：US12096621B2
公开(公告)日：2024-09-17
申请号：US17680208
申请日：2022-02-24
发明人： Wei Cheng Wu , Li-Feng Teng
CPC分类号： H10B41/00 , G11C16/0408 , H01L29/66825 , H01L29/788 , H10B12/09 , H10B12/50 , H10B99/00
摘要： Various embodiments of the present application are directed to an IC device and associated forming methods. In some embodiments, a memory region and a logic region are integrated in a substrate. A memory cell structure is disposed on the memory region. A plurality of logic devices disposed on a plurality of logic sub-regions of the logic region. A first logic device is disposed on a first upper surface of a first logic sub-region. A second logic device is disposed on a second upper surface of a second logic sub-region. A third logic device is disposed on a third upper surface of a third logic sub-region. Heights of the first, second, and third upper surfaces of the logic sub-regions monotonically decrease. By arranging logic devices on multiple recessed positions of the substrate, design flexibility is improved and devices with multiple operation voltages are better suited.
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公开(公告)号：US11917828B2
公开(公告)日：2024-02-27
申请号：US17314528
申请日：2021-05-07
发明人： Ting-Feng Liao , Mao-Yuan Weng , Kuang-Wen Liu
IPC分类号： H10B41/00 , H10B43/50 , H01L23/522 , H01L21/768 , H10B41/27 , H10B41/35 , H10B41/50 , H10B43/27 , H10B43/35
CPC分类号： H10B43/50 , H01L21/76877 , H01L23/5226 , H10B41/27 , H10B41/35 , H10B41/50 , H10B43/27 , H10B43/35
摘要： Methods, systems and apparatus for memory devices with multiple string select line (SSL) cuts are provided. In one aspect, a semiconductor device includes: a three-dimensional (3D) array of memory cells and a plurality of common source lines (CSLs) configured to separate the 3D array of memory cells into a plurality of portions. Each portion of the plurality of portions is between two adjacent CSLs and includes a plurality of conductive layers separated from each other by insulating layers and a plurality of vertical channels arranged orthogonally through the plurality of conductive layers and the insulating layers, each of the plurality of vertical channels including a string of memory cells. A top part of each portion of one or more portions includes at least two SSL cuts configured to separate the portion into multiple independent units, and each of the independent units is selectable by a corresponding SSL of multiple SSLs.
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公开(公告)号：US11818884B2
公开(公告)日：2023-11-14
申请号：US17545519
申请日：2021-12-08
发明人： Chien-Hsien Wu , Chun-Hung Lin , Kao-Tsair Tsai , Yao-Ting Tsai
IPC分类号： H01L21/3105 , H01L21/76 , H10B41/00 , H01L29/66
CPC分类号： H10B41/00 , H01L29/66825
摘要： A method for manufacturing a non-volatile memory device is provided. The method includes forming a trench through a sacrificial layer and extending into a substrate, filling a first insulating material into the trench, and implanting a dopant in the first insulating material by an implantation process. Then, the first insulating material is partially removed to form a first recess between the sacrificial layers. The lowest point of the first recess is lower than the top surface of the substrate. The method includes filling a second insulating material in the first recess and removing the sacrificial layer to form a second recess adjacent to the second insulating material. The method includes forming a first polycrystalline silicon layer in the second recess, and sequentially forming a dielectric layer and a second polycrystalline silicon layer on the first polycrystalline silicon layer.
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公开(公告)号：US20240063798A1
公开(公告)日：2024-02-22
申请号：US18501993
申请日：2023-11-04
发明人： Jin-Yuan Lee , Mou-Shiung Lin
IPC分类号： H03K19/1776 , H01L23/00 , H01L27/02 , H01L27/092 , H01L27/12 , H01L29/66 , H01L29/78 , H03K19/17724 , H10B41/00 , H10B41/30 , H10B61/00 , H10B63/00 , H10N50/10
CPC分类号： H03K19/1776 , H01L24/00 , H01L27/0207 , H01L27/0924 , H01L27/12 , H01L27/1203 , H01L29/66795 , H01L29/785 , H03K19/17724 , H10B41/00 , H10B41/30 , H10B61/00 , H10B63/00 , H10N50/10 , G11C7/00
摘要： A field-programmable-gate-array (FPGA) IC chip includes multiple first non-volatile memory cells in the FPGA IC chip, wherein the first non-volatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip, wherein the programmable logic block is configured to select, in accordance with its inputs, one from the resulting values into its output; and multiple second non-volatile memory cells in the FPGA IC chip, wherein the second non-volatile memory cells are configured to save multiple programming codes configured to control a switch of the FPGA IC chip.
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公开(公告)号：US20230307467A1
公开(公告)日：2023-09-28
申请号：US18200052
申请日：2023-05-22
发明人： Shunpei YAMAZAKI , Jun KOYAMA , Kiyoshi KATO
IPC分类号： H01L27/12 , H01L21/84 , H01L27/118 , H10B10/00 , H10B12/00 , H10B41/00 , H10B41/30 , H10B41/70 , H01L29/786 , H01L29/24
CPC分类号： H01L27/1255 , H01L21/84 , H01L27/11803 , H01L27/1225 , H10B10/00 , H10B10/125 , H10B12/00 , H10B12/05 , H10B12/30 , H10B41/00 , H10B41/30 , H10B41/70 , H01L29/7869 , H01L29/24 , G11C16/0433
摘要： An object of the present invention is to provide a semiconductor device having a novel structure in which in a data storing time, stored data can be stored even when power is not supplied, and there is no limitation on the number of writing. A semiconductor device includes a first transistor including a first source electrode and a first drain electrode; a first channel formation region for which an oxide semiconductor material is used and to which the first source electrode and the first drain electrode are electrically connected; a first gate insulating layer over the first channel formation region; and a first gate electrode over the first gate insulating layer. One of the first source electrode and the first drain electrode of the first transistor and one electrode of a capacitor are electrically connected to each other.
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