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    REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES
    1.
    发明申请
    REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES 有权

    公开(公告)号：US20220359020A1

    公开(公告)日：2022-11-10

    申请号：US17751131

    申请日：2022-05-23

    申请人： Micron Technology, Inc.

    发明人： Aaron Yip

    IPC分类号： G11C16/34 ,  G11C16/04 ,  G11C16/24 ,  G11C16/10

    摘要： Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.

    3D memory device including shared select gate connections between memory blocks
    2.
    发明授权
    3D memory device including shared select gate connections between memory blocks 有权

    公开(公告)号：US11164629B2

    公开(公告)日：2021-11-02

    申请号：US16921613

    申请日：2020-07-06

    申请人： Micron Technology, Inc.

    发明人： Aaron Yip

    IPC分类号： G11C16/04 ,  H01L27/11582 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  G11C16/14 ,  G11C16/08 ,  H01L27/11575

    摘要： Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line.

    Sense flags in a memory device
    3.
    发明授权
    Sense flags in a memory device 有权

    公开(公告)号：US11029861B2

    公开(公告)日：2021-06-08

    申请号：US16543743

    申请日：2019-08-19

    申请人： MICRON TECHNOLOGY, INC.

    发明人： Shafqat Ahmed ,  Khaled Hasnat ,  Pranav Kalavade ,  Krishna Parat ,  Aaron Yip ,  Mark A. Helm ,  Andrew Bicksler

    IPC分类号： G06F3/06 ,  G11C16/24 ,  G11C16/26 ,  G11C16/04 ,  G06F12/0804 ,  G06F13/28 ,  G06F12/0846

    摘要： Memory devices might be configured to perform methods including reading a first page of memory cells and flag data wherein the flag data indicates whether a second page of memory cells adjacent to the first page is programmed, and determining from the flag data whether to re-read the first page of memory cells with an adjusted read voltage; performing a sense operation on memory cells coupled to first data lines of a first array of memory cells and memory cells coupled to data lines of a second array of memory cells, and determining a program indication of memory cells coupled to second data lines from the sense operation performed on the memory cells coupled to the data lines of the second array of memory cells; and/or programming memory cells coupled to first data lines in a first array of memory cells, and programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in a second array of memory cells with flag data indicative of the memory cells coupled to the second data lines in the first array of memory cells being programmed.

    REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES
    8.
    发明申请
    REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES 审中-公开

    公开(公告)号：US20170178738A1

    公开(公告)日：2017-06-22

    申请号：US15451022

    申请日：2017-03-06

    申请人： Micron Technology, Inc.

    发明人： Aaron Yip

    IPC分类号： G11C16/34 ,  G11C16/10 ,  G11C16/24

    摘要： Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then he applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.

    Apparatuses and methods using dummy cells programmed to different states
    9.
    发明授权
    Apparatuses and methods using dummy cells programmed to different states 有权
    使用编程为不同状态的虚拟单元的设备和方法

    公开(公告)号：US09412451B2

    公开(公告)日：2016-08-09

    申请号：US14509953

    申请日：2014-10-08

    申请人： Micron Technology, Inc.

    发明人： Toru Tanzawa ,  Aaron Yip

    IPC分类号： G11C16/04 ,  G11C16/10

    CPC分类号： G11C16/28 ,  G11C7/02 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3427

    摘要： Apparatuses and methods for reducing capacitive loading are described. An example apparatus may include a plurality of memory subblocks of a memory block. A plurality of word lines may be associated with the plurality of subblocks. The word lines may be further associated with multiple strings within the subblocks. A subset of the word lines may be dummy word lines. The cells of the dummy word lines may be programmed to a plurality of states. The states may be configured to deactivate and/or float unselected strings in the subblocks during certain memory operations.

    摘要翻译： 描述了用于降低电容负载的装置和方法。 示例性装置可以包括存储器块的多个存储器子块。 多个字线可以与多个子块相关联。 字线可以进一步与子块内的多个字符串相关联。 字线的子集可以是虚拟字线。 虚拟字线的单元可以被编程为多个状态。 可以将状态配置为在某些存储器操作期间停用和/或浮动子块中未选择的字符串。

    SYSTEMS WITH MEMORY SEGMENTATION AND SYSTEMS WITH BIASING LINES TO RECEIVE SAME VOLTAGES DURING ACCESSING
    10.
    发明申请
    SYSTEMS WITH MEMORY SEGMENTATION AND SYSTEMS WITH BIASING LINES TO RECEIVE SAME VOLTAGES DURING ACCESSING 有权
    具有存储分段和系统的系统，具有接收线路中的接收电压的偏移线

    公开(公告)号：US20150103578A1

    公开(公告)日：2015-04-16

    申请号：US14570254

    申请日：2014-12-15

    申请人： MICRON TECHNOLOGY, INC.

    发明人： Aaron Yip

    IPC分类号： G11C5/06 ,  G11C13/00

    CPC分类号： G11C5/06 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/72

    摘要： Memory devices, memory arrays, and methods of operation of memory arrays with segmentation. Segmentation elements can scale with the memory cells, and may be uni-directional or bi-directional diodes. Biasing lines in the array allow biasing of selected and unselected select devices and segmentation elements with any desired bias, and may use biasing devices of the same construction as the segmentation elements.

    摘要翻译： 存储器件，存储器阵列以及具有分段的存储器阵列的操作方法。 分割元件可以与存储器单元成比例，并且可以是单向或双向二极管。 阵列中的偏置线允许以任何所希望的偏置来偏移选定和未选择的选择装置和分割元件，并且可以使用与分割元件相同结构的偏置装置。