-
公开(公告)号：US20240194257A1
公开(公告)日：2024-06-13
申请号：US18581340
申请日：2024-02-19
Inventor： Elia Ambrosi , Cheng-Hsien Wu , Hengyuan Lee , Chien-Min Lee , Xinyu BAO
IPC: G11C13/00
CPC classification number: G11C13/003 , G11C2213/72
Abstract: First fire operations for an ovonic threshold switch (OTS) selector is provided. A first fire operation includes setting a peak amplitude of a voltage pulse, and performing at least one cycle, including: providing the voltage pulse to the OTS selector; sensing an output current passing through the OTS selector in response to the received voltage pulse; comparing a peak amplitude of the voltage pulse with a maximum peak amplitude ensuring initialization of the OTS selector; ending the first fire operation if the peak amplitude reaches the maximum peak amplitude; comparing the output current with a target current indicative of initialization of the OTS selector if the peak amplitude is lower than the maximum peak amplitude; ending the first fire operation if the output current reaches the target current; and setting another voltage pulse with a greater peak amplitude if the output current is lower than the target current.
-
公开(公告)号：US11985909B2
公开(公告)日：2024-05-14
申请号：US16435875
申请日：2019-06-10
Applicant: Intel Corporation
Inventor： Elijah Karpov , Mauro Kobrinsky
CPC classification number: H10N70/231 , G11C13/0004 , G11C13/0069 , G11C13/0097 , H10B63/20 , H10B63/24 , H10B63/30 , H10N70/826 , H10N70/841 , H10N70/8828 , G11C13/004 , G11C2013/0092 , G11C2213/52 , G11C2213/72 , G11C2213/79
Abstract: Embodiments disclosed herein include memory bitcells and methods of forming such memory bitcells. In an embodiment, the memory bitcell is part of an embedded DRAM (eDRAM) memory device. In an embodiment, the memory bitcell comprises a substrate and a storage element embedded in the substrate. In an embodiment, the storage element comprises a phase changing material that comprises a binary alloy. In an embodiment, the memory bitcell further comprises a first electrode over a first surface of the storage element, and a second electrode over a second surface of the storage element.
-
公开(公告)号：US11984163B2
公开(公告)日：2024-05-14
申请号：US17665123
申请日：2022-02-04
Applicant: HEFEI RELIANCE MEMORY LIMITED
Inventor： Deepak Chandra Sekar , Gary Bela Bronner , Frederick A. Ware
CPC classification number: G11C13/0069 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C13/004 , G11C13/0097 , G11C2213/15 , G11C2213/72 , G11C2213/74 , G11C2213/75 , G11C2213/78 , G11C2213/79
Abstract: A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.
-
公开(公告)号：US11984161B2
公开(公告)日：2024-05-14
申请号：US17824826
申请日：2022-05-25
Applicant: Micron Technology, Inc.
Inventor： Srivatsan Venkatesan , Sundaravadivel Rajarajan , Iniyan Soundappa Elango , Robert Douglas Cassel
CPC classification number: G11C13/0059 , G11C13/0004 , G11C13/003 , H10B63/24 , H10B63/80 , H10N70/063 , H10N70/231 , H10N70/882 , G11C2213/72
Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. Spike current suppression is implemented by charge screening structures. The charge screening structures are formed by laterally integrating insulating layers into selected interior regions of the left and/or right portions of the access line. The insulating layers vertically separate the access line into top and bottom conductive portions above and below the insulating layers. For memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the top or bottom conductive portion. During a spike discharge, charge is choked by this higher resistance path. This suppresses spike current that occurs when the memory cell is selected.
-
公开(公告)号：US11967375B2
公开(公告)日：2024-04-23
申请号：US17529261
申请日：2021-11-18
Inventor： Hung-Li Chiang , Chao-Ching Cheng , Tzu-Chiang Chen , Yu-Sheng Chen , Hon-Sum Philip Wong
CPC classification number: G11C13/003 , G11C13/004 , H10B63/24 , G11C2213/15 , G11C2213/72
Abstract: A memory device that includes at least one memory cell is introduced. Each of the at least one memory cell is coupled to a bit line and a word line. Each of the at least one memory cell includes a memory element and a selector element, in which the memory element is configured to store data of the at least one memory cell. The selector element is coupled to the memory element in series and is configured to select the memory element for a read operation and amplify the data stored in the memory element in the read operation.
-
Patent Agency Ranking
公开(公告)号：US20230326523A1
公开(公告)日：2023-10-12
申请号：US18188332
申请日：2023-03-22
Applicant: SK hynix Inc. , Foundation for Research and Business, Seoul National University of Science and Technology , INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY ERICA CAMPUS
Inventor： Tae Jung HA , Soo Gil KIM , Jeong Hwan SONG , Byung Joon CHOI , Ha Young LEE
CPC classification number: G11C13/003 , G11C11/1659 , G11C2213/72
Abstract: Operating a selector device that controls access of a signal to a memory element may comprise applying a main operating voltage pulse and a refresh voltage pulse to the selector device. The refresh voltage pulse and main operating voltage pulse have opposite polarities. A magnitude of the main operating voltage pulse is greater than or equal to a threshold voltage for turning on the selector device, and a maximum magnitude of the refresh voltage pulse is less than the threshold voltage. The refresh voltage pulse reduces a difference between the threshold voltage and a turn-off voltage of the selector device, and may be applied immediately before or immediately after the main operating voltage pulse. An electronic circuit may include the selector device and a driving circuit for apply the pulses. A nonvolatile memory may include the driving circuit and a plurality of nonvolatile memory elements each including a selector device.
-
公开(公告)号：US20230200267A1
公开(公告)日：2023-06-22
申请号：US18172385
申请日：2023-02-22
Applicant: International Business Machines Corporation
Inventor： Kevin W. Brew , Injo Ok , Jin Ping Han , Timothy Mathew Philip , Matthew Joseph BrightSky , Nicole Saulnier
CPC classification number: H10N70/231 , G11C11/54 , H10N70/826 , H10B63/24 , G11C13/0004 , H10N70/8413 , G06N3/065 , G11C2213/72
Abstract: A phase change memory (PCM) cell comprises a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, a first phase change layer positioned between the first electrode and the second electrode and being comprised of a first phase change material, and a second phase change layer positioned between the first electrode and the second electrode and being comprised of a second phase change material. The first phase change material has a first resistivity, the second phase change material has a second resistivity, and wherein the first resistivity is at least two times the second resistivity.
-
公开(公告)号：US20190172531A1
公开(公告)日：2019-06-06
申请号：US16034850
申请日：2018-07-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Chea Ouk Lim , Tae Hui Na , Jung Sunwoo , Yong Jun Lee
IPC: G11C13/00
CPC classification number: G11C13/0004 , G11C13/003 , G11C13/0033 , G11C13/004 , G11C13/0069 , G11C2013/0047 , G11C2013/0057 , G11C2213/15 , G11C2213/72
Abstract: A memory device including: a memory cell array, including a memory cell having a switch element and a data storage element connected to the switch element, wherein the data storage element has a phase change material; and a memory controller for inputting a first read current to the memory cell to detect a first read voltage, inputting a second read current to the memory cell to detect a second read voltage, and inputting a compensation current to the memory cell, wherein the compensation current lowers a resistance value of the data storage element, the compensation current is input when a first state of the memory cell is different from a second state of the memory cell, the first state is determined using the first read voltage and the second state is determined using the second read voltage.
-
9.发明申请公开(公告)号：US20180364931A1
公开(公告)日：2018-12-20
申请号：US16018837
申请日：2018-06-26
Applicant: UNITY SEMICONDUCTOR CORPORATION
Inventor： Chang Hua Siau
IPC: G06F3/06 , G11C11/419 , G11C13/00 , G11C5/06 , G11C8/08
CPC classification number: G06F3/0625 , G06F3/061 , G06F3/0655 , G06F3/0688 , G11C5/06 , G11C8/08 , G11C11/419 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0021 , G11C13/0023 , G11C13/003 , G11C13/0038 , G11C13/0069 , G11C13/0097 , G11C2213/72
Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.
-
公开(公告)号：US20180358056A1
公开(公告)日：2018-12-13
申请号：US15854551
申请日：2017-12-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kilho LEE , Gwanhyeob KOH , Junhee LIM , Hongsoo KIM , Chang-hoon JEON
IPC: G11C5/06 , G11C16/04 , G11C11/16 , H01L25/18 , H01L27/1157 , H01L27/22 , H01L27/11573 , H01L43/10
CPC classification number: G11C5/06 , G11C11/005 , G11C11/161 , G11C13/0002 , G11C13/0004 , G11C16/0483 , G11C2213/72 , G11C2213/76 , H01L25/18 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L27/222 , H01L43/10
Abstract: A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.
-
-
-
-
-
-
-
-
-
Search Results
2458
records
(took 0.025 seconds)
