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公开(公告)号：US11984157B2
公开(公告)日：2024-05-14
申请号：US17666311
申请日：2022-02-07
Applicant: Michael Kozicki
Inventor： Michael Kozicki
IPC: G11C13/00 , H01L23/40 , H01L23/528 , H10B63/00 , H10N70/20
CPC classification number: G11C13/0011 , H01L23/40 , H01L23/528 , H10B63/00 , H10N70/245
Abstract: Programmable interposers for connecting integrated circuits, methods for programming programmable interposers, and integrated circuit packaging are provided. The programmable interposers are electrically reconfigurable to allow custom system-in-package (SiP) operation and configuration, field configurability, and functional obfuscation for secure integrated circuits fabricated in non-trusted environments. The programmable interposer includes, in one implementation, an interposer substrate and a programmable metallization cell (PMC) switch. The PMC switch is formed on the interposer substrate and is coupled between a signal input and a signal output. The PMC switch is electrically configurable between a high resistance state and a low resistance state.
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公开(公告)号：US11963465B2
公开(公告)日：2024-04-16
申请号：US18114419
申请日：2023-02-27
Applicant: Hefei Reliance Memory Limited
Inventor： Zhichao Lu , Gary Bela Bronner
CPC classification number: H10N70/24 , G11C13/0007 , G11C13/0011 , H10N70/021 , H10N70/041 , H10N70/245 , H10N70/826 , H10N70/841 , H10N70/881 , H10N70/8825 , H10N70/8833 , G11C2213/50 , G11C2213/51
Abstract: Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a filament and one or more lateral regions including a doping material that are between a top region and a bottom region of the switching layer. The RRAM further includes a top electrode disposed above the switching layer.
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公开(公告)号：US11845870B2
公开(公告)日：2023-12-19
申请号：US17111353
申请日：2020-12-03
Applicant: BOISE STATE UNIVERSITY
Inventor： Maria Mitkova , Al-Amin Ahmed Simon , Shah Mohammad Rahmot Ullah , Bahareh Badamchi , Harish Subbaraman
IPC: G11C13/00 , C09D11/03 , B33Y70/10 , C03C3/32 , C03C1/00 , C03B19/12 , C03B5/225 , B33Y40/10 , B33Y10/00 , C03C21/00 , C09D11/38 , B33Y30/00 , B82Y30/00 , B82Y40/00
CPC classification number: C09D11/03 , B33Y10/00 , B33Y40/10 , B33Y70/10 , C03B5/2252 , C03B19/12 , C03C1/006 , C03C3/321 , C03C21/005 , C09D11/38 , G11C13/0011 , B33Y30/00 , B82Y30/00 , B82Y40/00 , C03C2203/50 , C03C2204/00 , G11C2213/30
Abstract: A device formation method may include printing a chalcogenide glass ink onto a surface to form a chalcogenide glass layer, where the chalcogenide glass ink comprises chalcogenide glass and a fluid medium. The method may further include sintering the chalcogenide glass layer at a first temperature for a first duration. The method may also include annealing the chalcogenide glass layer at a second temperature for a second duration. A device may include a substrate and a printed chalcogenide glass layer on the substrate, where the printed chalcogenide glass layer includes annealed chalcogenide glass, and where the printed chalcogenide glass layer is free from cracks.
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公开(公告)号：US11837286B2
公开(公告)日：2023-12-05
申请号：US18046393
申请日：2022-10-13
Applicant: Micron Technology, Inc.
Inventor： John Christopher Sancon
CPC classification number: G11C13/003 , G11C13/0026 , G11C13/0028 , G11C13/0004 , G11C13/0011
Abstract: Memory devices have an array of elements in two or more dimensions. The memory devices use multiple access lines arranged in a grid to access the memory devices. Memory cells are located at intersections of the access lines in the grid. Drivers are used for each access line and configured to transmit a corresponding signal to respective memory cells of the plurality of memory cells via a corresponding access line. The memory devices also include compensation circuitry configured to determine which driving access lines driving a target memory cell of the plurality of memory cells has the most distance between the target memory cell and a respective driver. The plurality of access lines comprise the driving access lines. The compensation circuitry also is configured to output compensation values to adjust the voltages of the driving access lines based on a polarity of the voltage of the longer driving access line.
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公开(公告)号：US20230354618A1
公开(公告)日：2023-11-02
申请号：US18347794
申请日：2023-07-06
Inventor： Chin-Chieh Yang , Chih-Yang Chang , Wen-Ting Chu , Yu-Wen Liao
CPC classification number: H10B63/82 , G11C13/0011 , G11C13/0069 , H10B63/30 , H10B63/80 , H10N70/20 , H10N70/24 , H10N70/063 , H10N70/826 , H10N70/841 , H10N70/8833 , H10N70/8836 , G11C13/0023 , G11C13/004 , G11C2213/79 , H01L23/5226
Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element and a second RRAM element over a substrate. A conductive element is arranged below the first RRAM element and the second RRAM element. The conductive element electrically couples the first RRAM element to the second RRAM element. An upper insulating layer continuously extends over the first RRAM element and the second RRAM element. An upper inter-level dielectric (ILD) structure laterally surrounds the first RRAM element and the second RRAM element. The upper insulating layer separates the first RRAM element and the second RRAM element from the upper ILD structure.
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Patent Agency Ranking
公开(公告)号：US11800823B2
公开(公告)日：2023-10-24
申请号：US17165088
申请日：2021-02-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Fa-Shen Jiang , Hsing-Lien Lin
CPC classification number: H10N70/245 , G11C13/0011 , H10N70/063 , H10N70/8265 , H10N70/841 , H10N70/8613
Abstract: Some embodiments relate to a method for manufacturing a memory device. The method includes forming a bottom electrode over a substrate. A heat dispersion layer is formed over the bottom electrode. A dielectric layer is formed over the heat dispersion layer. A top electrode is formed over the dielectric layer. The heat dispersion layer comprises a first dielectric material.
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公开(公告)号：US20230337557A1
公开(公告)日：2023-10-19
申请号：US18336088
申请日：2023-06-16
Inventor： Mauricio Manfrini , Chung-Te Lin , Gerben Doornbos , Marcus Johannes Henricus van Dal
CPC classification number: H10N70/823 , G11C13/0007 , G11C13/0011 , H10B63/30 , H10N70/021 , H10N70/841 , H10N70/883
Abstract: Some embodiments relate to an integrated chip including a memory device. The memory device includes a bottom electrode disposed over a semiconductor substrate. An upper electrode is disposed over the bottom electrode. An intercalated metal/dielectric structure is sandwiched between the bottom electrode and the upper electrode. The intercalated metal/dielectric structure comprises a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.
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公开(公告)号：US20230253039A1
公开(公告)日：2023-08-10
申请号：US17842989
申请日：2022-06-17
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu LIN , Feng-Min LEE , Ming-Hsiu LEE
CPC classification number: G11C13/0033 , G11C13/004 , G11C13/0011 , G11C13/0069 , H01L45/085 , H01L45/1266
Abstract: A memory device and a method for operating the same are provided. The memory device includes a plurality of resistive memory cells and a control circuitry electrically connected to the plurality of resistive memory cells. The control circuitry provides operation modes to operate the plurality of resistive memory cells. The operation modes include a first program operation and a refresh operation. The first program operation includes applying a first program bias voltage to a selected resistive memory cell of the plurality of resistive memory cells to establish a low-resistance state in the selected resistive memory cell. The first program operation establishes a first threshold voltage in the memory device. The refresh operation includes applying a refresh bias voltage to the selected resistive memory cell to refresh the selected resistive memory cell. An absolute value of the refresh bias voltage is greater than the first threshold voltage.
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公开(公告)号：US20190198759A1
公开(公告)日：2019-06-27
申请号：US16322344
申请日：2017-07-12
Inventor： Jin Pyo HONG , Gwang Ho BAEK , Ah Rahm LEE , Tea Yoon KIM
CPC classification number: H01L45/1266 , G11C13/0011 , H01L27/2454 , H01L29/417 , H01L29/66 , H01L29/732 , H01L45/00 , H01L45/1206 , H01L45/1233 , H01L45/145 , H01L45/1658
Abstract: Disclosed are a switching atomic transistor with a diffusion barrier layer and a method of operating the same. By introducing a diffusion barrier layer in an intermediate layer having a resistance change characteristic, it is possible to minimize variation in the entire number of ions in the intermediate layer involved in operation of the switching atomic transistor or to eliminate the variation to maintain stable operation of the switching atomic transistor. In addition, it is possible to stably implement a multi-level cell of a switching atomic transistor capable of storing more information without increasing the number of memory cells. Also, disclosed are a vertical atomic transistor with a diffusion barrier layer and a method of operating the same. By producing an ion channel layer in a vertical structure, it is possible to significantly increase transistor integration.
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10.发明申请公开(公告)号：US20190189689A1
公开(公告)日：2019-06-20
申请号：US16283645
申请日：2019-02-22
Applicant: Micron Technology, Inc.
Inventor： Zengtao T. Liu
CPC classification number: H01L27/249 , G11C13/0002 , G11C13/0011 , G11C2213/71 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1253 , H01L45/14 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1675 , H01L45/1683
Abstract: An array of vertically stacked tiers of memory cells includes a plurality of horizontally oriented access lines within individual tiers of memory cells and a plurality of horizontally oriented global sense lines elevationally outward of the tiers. A plurality of select transistors is elevationally inward of the tiers. A plurality of pairs of local first and second vertical lines extends through the tiers. The local first vertical line within individual of the pairs is in conductive connection with one of the global sense lines and in conductive connection with one of the two source/drain regions of one of the select transistors. The local second vertical line within individual of the pairs is in conductive connection with another of the two source/drain regions of the one select transistor. Individual of the memory cells include a crossing one of the local second vertical lines and one of the horizontal access lines and programmable material there-between. Other aspects and implementations, including methods, are disclosed.
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