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公开(公告)号：US20240074333A1
公开(公告)日：2024-02-29
申请号：US17893651
申请日：2022-08-23
Applicant: International Business Machines Corporation
Inventor： Carl Radens , Ruilong Xie , Kangguo Cheng , Julien Frougier , Juntao Li
CPC classification number: H01L45/06 , H01L23/481 , H01L27/2454 , H01L45/1206 , H01L45/1286
Abstract: A semiconductor structure is provided in which a phase change memory (PCM) device region including a PCM is located in a back side of a wafer. A PCM device back side source/drain contact structure connects the PCM to a first source/drain structure of a first field effect transistor (FET) that is present in a front side of the wafer, the second source/drain structure of the first FET is connected to a front side BEOL structure by a front side source/drain contact structure. A logic device region and/or an analog device region can be located laterally adjacent to the PCM device region. A back side power distribution network can be present in the logic device region and/or an analog device region.
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公开(公告)号：US20240015965A1
公开(公告)日：2024-01-11
申请号：US18073908
申请日：2022-12-02
Applicant: SK hynix Inc.
Inventor： Ga Ram CHOI , Dae Hyun KIM , Changhan Kim
IPC: H01L27/11582 , H01L27/11556 , H01L27/11597 , H01L27/24
CPC classification number: H01L27/11582 , H01L27/11556 , H01L27/11597 , H01L27/2454
Abstract: There are provided a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a doped semiconductor layer including an upper surface facing a first direction, a multifunctional stack including a plurality of interlayer insulating layers and a plurality of conductive layers stacked alternately with each other in the first direction above the doped semiconductor layer, the multifunctional stack including a groove, a liner insulating layer on a bottom surface of the groove, a liner semiconductor layer on the liner insulating layer, and a first electrode and a second electrode spaced apart from each other in the groove and extending in the first direction from the liner semiconductor layer.
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公开(公告)号：US20230292532A1
公开(公告)日：2023-09-14
申请号：US17875400
申请日：2022-07-27
Applicant: SK hynix Inc.
Inventor： Woo Cheol LEE
CPC classification number: H01L27/2454 , H01L27/2481 , H01L45/146 , H01L45/1206
Abstract: A semiconductor device according to an embodiment of the present disclosure includes a substrate, a gate electrode layer disposed over the substrate, a gate dielectric layer disposed on the gate electrode layer, a channel electrode layer disposed on the gate dielectric layer, a threshold switching layer disposed on the channel electrode layer, and a source electrode layer and a drain electrode layer that are disposed on the threshold switching layer to be spaced apart from each other.
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公开(公告)号：US20230284464A1
公开(公告)日：2023-09-07
申请号：US17939859
申请日：2022-09-07
Applicant: Kioxia Corporation
Inventor： Hidehiro SHIGA , Daisaburo TAKASHIMA
CPC classification number: H01L27/249 , G11C11/1673 , G11C11/1675 , G11C13/004 , G11C13/0069 , H01L27/228 , H01L27/2454 , H01L43/02 , H01L45/126 , G11C2213/71 , G11C2213/75 , G11C2213/79
Abstract: According to a certain embodiment, the 3D stacked semiconductor memory includes: a first electrode line extending in a first direction orthogonal to the semiconductor substrate; a second electrode line adjacent to the first electrode line in a second direction orthogonal to the first direction, and extending in the first direction; a first variable resistance film extending in the first direction and in contact with the second electrode line; a first semiconductor film in contact with the first variable resistance film and the first electrode line; a first potential applying electrode extending in the second direction and in contact with a first insulator layer; a second semiconductor film in contact with a second variable resistance film and the first electrode line; and a second potential applying electrode extending in the second direction and in contact with a second insulator layer. The first and second potential applying electrodes are electrically different nodes.
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5.发明申请公开(公告)号：US20190214305A1
公开(公告)日：2019-07-11
申请号：US15863000
申请日：2018-01-05
Applicant: International Business Machines Corporation
Inventor： Ruqiang Bao , Shogo Mochizuki , Choonghyun Lee , Chun Wing Yeung
IPC: H01L21/8238 , H01L27/092 , H01L21/308
CPC classification number: H01L21/82385 , H01L21/28026 , H01L21/3081 , H01L21/3086 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/0928 , H01L27/2454 , H01L29/66666 , H01L29/7827 , H01L29/7889 , H01L29/8083
Abstract: Techniques for forming VFETs having different gate lengths (and optionally different gate pitch and/or gate oxide thickness) on the same wafer are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a wafer including a first fin(s) patterned to a first depth and a second fin(s) patterned to a second depth, wherein the second depth is greater than the first depth; forming bottom source/drains at a base of the fins; forming bottom spacers on the bottom source/drains; forming gates alongside the fins, wherein the gates formed alongside the first fin(s) have a first gate length Lg1, wherein the gates formed alongside the second fin(s) have a second gate length Lg2, and wherein Lg1
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Patent Agency Ranking
公开(公告)号：US20180261766A1
公开(公告)日：2018-09-13
申请号：US15452373
申请日：2017-03-07
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Ming-Che Wu , Deepak Kamalanathan , Juan Saenz , Tanmay Kumar
CPC classification number: H01L45/1608 , G11C7/18 , G11C8/14 , G11C13/0007 , G11C2213/35 , G11C2213/71 , H01L27/2436 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1206 , H01L45/1233 , H01L45/124 , H01L45/146 , H01L45/16
Abstract: A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The word line includes a first portion and a second portion including an electrically conductive carbon-containing material. The nonvolatile memory material includes a semiconductor material layer and a conductive oxide material layer, with the semiconductor material layer disposed adjacent the second portion of the word line.
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公开(公告)号：US20180233664A1
公开(公告)日：2018-08-16
申请号：US15695450
申请日：2017-09-05
Applicant: Toshiba Memory Corporation
Inventor： Toshiyuki IWAMOTO
CPC classification number: H01L45/08 , G11C13/0007 , G11C13/0069 , G11C2013/0071 , G11C2213/51 , G11C2213/71 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L45/1226 , H01L45/1253 , H01L45/146
Abstract: A memory device includes a first interconnection, a second interconnection including a first material, and a variable resistance film between the first interconnection and the second interconnection The variable resistance film includes a first layer including a second material, a second layer between the first layer and the second interconnection and including a third material, a third layer between the first layer and the second layer and including a fourth material, and a fourth layer between the second layer and the second interconnection and including a fifth material. A reactivity of the fourth material with the second material is less than a reactivity of the third material and the second material, and a reactivity of the fifth material with the first material is less than a reactivity of the third material with the first material.
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8.发明申请公开(公告)号：US20180158873A1
公开(公告)日：2018-06-07
申请号：US15367791
申请日：2016-12-02
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Michiaki SANO , Zhen CHEN , Tetsuya YAMADA , Akira NAKADA , Yasuke ODA , Manabu HAYASHI , Shigenori SATO
IPC: H01L27/24 , H01L27/115 , H01L45/00
CPC classification number: H01L45/16 , H01L27/11565 , H01L27/11575 , H01L27/11582 , H01L27/2409 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146
Abstract: A wedge-shaped contact region can be employed to provide electrical contacts to multiple electrically conductive layers in a three-dimensional device structure. A cavity including a generally wedge-shaped region and a primary region is formed in a dielectric matrix layer over a support structure. An alternating stack of insulating layers and electrically conductive layers is formed by a series of conformal deposition processes in the cavity and over the dielectric matrix layer. The alternating stack can be planarized employing the top surface of the dielectric matrix layer as a stopping layer. A tip portion of each electrically conductive layer within remaining portions of the alternating stack is laterally offset from the tip of the generally wedge-shaped region by a respective lateral offset distance along a lateral protrusion direction. Contact via structures can be formed on the tip portions of the electrically conductive layers to provide electrical contact.
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公开(公告)号：US09991368B2
公开(公告)日：2018-06-05
申请号：US15371801
申请日：2016-12-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Wei Ting , Chun-Yang Tsai , Kuo-Ching Huang
CPC classification number: H01L29/732 , G11C11/161 , G11C11/40 , G11C13/0002 , G11C13/003 , G11C13/0069 , G11C2213/79 , H01L27/226 , H01L27/228 , H01L27/2436 , H01L27/2445 , H01L27/2454 , H01L29/66272 , H01L29/66333 , H01L29/82 , H01L45/04
Abstract: Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled to a source line of the memory device. A base region is formed over the collector region and has a second conductivity type. A gate structure is coupled to the base region and acts as a shared word line for first and second neighboring memory cells of the memory device. First and second emitter regions are formed over the base region and have the first conductivity type. The first and second emitter regions are arranged on opposite sides of the gate structure. First and second contacts extend upwardly from the first and second emitter regions, respectively, and couple the first and second emitter regions to first and second data storage elements, respectively, of the first and second neighboring memory cells, respectively.
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公开(公告)号：US20180138242A1
公开(公告)日：2018-05-17
申请号：US15858811
申请日：2017-12-29
Applicant: Micron Technology, Inc.
Inventor： Samuele Sciarrillo
CPC classification number: H01L27/2481 , H01L27/2427 , H01L27/2445 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1675
Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls. The memory device additionally comprises first protective dielectric insulating materials formed on a lower portion of the first pair of sidewalls and an isolation dielectric formed on the first protective dielectric insulating material and further formed on an upper portion of the first pair of sidewalls.
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