公开(公告)号：US12087816B2

公开(公告)日：2024-09-10

申请号：US17716555

申请日：2022-04-08

Applicant: Infineon Technologies Dresden GmbH & Co. KG

Inventor： Hans-Juergen Thees ,  Stefan Loesch ,  Marc Probst ,  Tom Richter ,  Olaf Storbeck

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/0696 ,  H01L29/66333 ,  H01L29/7395

Abstract: A power semiconductor device includes a control cell for controlling a load current and electrically connected to a load terminal structure on one side and to a drift region on another side. The drift region includes dopants of a first conductivity type. The control cell includes: a mesa extending along a vertical direction and including a contact region having dopants of the first or second conductivity type and electrically connected to the load terminal structure, and a channel region coupled to the drift region; a control electrode configured to control a conduction channel in the channel region; and a contact plug including at least one of a doped semiconductive material or metal, and arranged in contact with the contact region. An electrical connection between the contact region and load terminal structure is established by the contact plug, a portion of which horizontally projects beyond lateral boundaries of the mesa.

公开(公告)号：US20240162284A1

公开(公告)日：2024-05-16

申请号：US18472175

申请日：2023-09-21

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hiroshi TAKISHITA ,  Yuusuke OOSHIMA ,  Takashi YOSHIMURA ,  Shuntaro YAGUCHI

IPC: H01L29/06 ,  H01L29/36 ,  H01L29/66 ,  H01L29/739 ,  H01L29/861

CPC classification number: H01L29/0615 ,  H01L29/0684 ,  H01L29/36 ,  H01L29/66333 ,  H01L29/7395 ,  H01L29/8611

Abstract: A manufacturing method of a semiconductor device including a buffer region in a semiconductor substrate is provided, comprising: obtaining a substrate concentration index related to at least one of an oxygen chemical concentration or a carbon chemical concentration included in the semiconductor substrate; classifying the substrate concentration index as any index range among a predetermined plurality of index ranges; determining an acceleration energy of hydrogen ions to be implanted into the semiconductor substrate to an acceleration energy that is preset to correspond to the classified index range; and forming a buffer region of the semiconductor device by implanting hydrogen ions into the semiconductor substrate with the determined acceleration energy.

公开(公告)号：US20240047200A1

公开(公告)日：2024-02-08

申请号：US18487724

申请日：2023-10-16

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Yuichi ONOZAWA

IPC: H01L21/02 ,  H01L29/36 ,  H01L29/10 ,  H01L29/739 ,  H01L21/263 ,  H01L29/32 ,  H01L29/66 ,  H01L29/861 ,  H01L29/06 ,  H01L29/167 ,  H01L29/868

CPC classification number: H01L21/02351 ,  H01L29/36 ,  H01L29/365 ,  H01L29/1095 ,  H01L29/7397 ,  H01L21/263 ,  H01L29/32 ,  H01L29/66136 ,  H01L29/66348 ,  H01L29/8611 ,  H01L29/0619 ,  H01L29/167 ,  H01L21/02304 ,  H01L29/66333 ,  H01L29/7395 ,  H01L29/868 ,  H01L29/402

Abstract: A semiconductor device is disclosed in which proton implantation is performed a plurality of times to form a plurality of n-type buffer layers in an n-type drift layer at different depths from a rear surface of a substrate. The depth of the n-type buffer layer, which is provided at the deepest position from the rear surface of the substrate, from the rear surface of the substrate is more than 15 μm. The temperature of a heat treatment which is performed in order to change a proton into a donor and to recover a crystal defect after the proton implantation is equal to or higher than 400° C. In a carrier concentration distribution of the n-type buffer layer, a width from the peak position of carrier concentration to an anode is more than a width from the peak position to a cathode.

公开(公告)号：US20240030323A1

公开(公告)日：2024-01-25

申请号：US18352667

申请日：2023-07-14

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Hans-Jürgen Thees ,  Thorsten Arnold

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7397 ,  H01L29/66333 ,  H01L29/4236

Abstract: A power semiconductor device and a method of producing a power semiconductor device are presented. The power semiconductor device is, for example, embodied as an IGBT and includes a deep cross trench which extends below trenches that include, e.g., control and source trench electrodes.

公开(公告)号：US11848354B2

公开(公告)日：2023-12-19

申请号：US17401827

申请日：2021-08-13

Applicant: Infineon Technologies AG

Inventor： Roman Baburske ,  Philip Christoph Brandt ,  Johannes Georg Laven

IPC: H01L29/06 ,  H01L27/07 ,  H01L29/66 ,  H01L21/22 ,  H01L27/06 ,  H01L29/08 ,  H01L29/739 ,  H01L29/861 ,  H01L29/16 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/0638 ,  H01L21/221 ,  H01L27/0664 ,  H01L27/0727 ,  H01L29/0623 ,  H01L29/0834 ,  H01L29/66136 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/861 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4238

Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminals. The body includes: at least a diode structure configured to conduct a load current between the terminals and including an anode port electrically connected to the first load terminal and a cathode port electrically connected to the second load terminal; and drift and field stop regions of the same conductivity type. The cathode port includes first port sections and second port sections with dopants of the opposite conductivity type. A transition between each of the second port sections and the field stop region forms a respective pn-junction that extends along a first lateral direction. A lateral separation distance between immediately adjacent ones of second port sections in a second group is smaller than in a first group.

公开(公告)号：US20230402511A1

公开(公告)日：2023-12-14

申请号：US18455643

申请日：2023-08-25

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Motoyoshi KUBOUCHI ,  Takashi YOSHIMURA ,  Yuki SAWA ,  Shogo YAMAGUCHI

IPC: H01L29/32 ,  H01L29/739 ,  H01L29/06 ,  H01L21/265 ,  H01L21/322 ,  H01L29/861 ,  H01L29/66

CPC classification number: H01L29/32 ,  H01L29/7395 ,  H01L29/0603 ,  H01L21/265 ,  H01L21/322 ,  H01L29/8613 ,  H01L29/66333

Abstract: Provided is a semiconductor device including a drift region, a buffer region which is provided in a back surface side of a semiconductor substrate relative to the drift region and has a first peak of a doping concentration, and a first lattice defect region which is provided in a front surface side of the semiconductor substrate relative to the first peak in a depth direction of the semiconductor substrate, in which the buffer region has a hydrogen peak which is provided in the front surface side of the semiconductor substrate relative to the first lattice defect region, and an integrated concentration obtained by integrating the doping concentration in a direction from an upper end of the drift region to the hydrogen peak in the depth direction of the semiconductor substrate is equal to or larger than a critical integrated concentration.

公开(公告)号：US20230369445A1

公开(公告)日：2023-11-16

申请号：US17744604

申请日：2022-05-13

Applicant: Wolfspeed, Inc.

Inventor： Daniel Jenner Lichtenwalner ,  Sei-Hyung Ryu

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/739

CPC classification number: H01L29/66333 ,  H01L29/1608 ,  H01L29/7397

Abstract: A vertical semiconductor and method for fabricating the same is disclosed. In one embodiment, fabrication entails providing a precursor comprising a substrate and a drift region over the substrate. A plurality of trenches is etched into the drift region from a top surface of the drift region such that a plurality of mesas remains in an upper portion of the drift region. The plurality of trenches is then filled with a first material. A vertical semiconductor device includes a plurality of mesas extends from an upper portion of the drift region, wherein there are no regrowth interfaces between the drift region and the plurality of mesas. A first material fills the trenches between each one of the plurality of mesas. At least one first contact over at least one of the plurality of mesas. At least one second contact over a bottom surface of the substrate.

公开(公告)号：US11742384B2

公开(公告)日：2023-08-29

申请号：US17217251

申请日：2021-03-30

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Christian Jaeger ,  Moriz Jelinek ,  Daniel Schloegl ,  Benedikt Stoib

IPC: H01L29/08 ,  H01L29/739 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L21/322 ,  H01L29/10

CPC classification number: H01L29/0834 ,  H01L21/26513 ,  H01L21/3221 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/7395

Abstract: A vertical power semiconductor device is proposed. The vertical power semiconductor device includes a semiconductor body having a first main surface and a second main surface opposite to the first main surface along a vertical direction. The vertical power semiconductor device further includes a drift region in the semiconductor body. The drift region includes platinum atoms. The vertical power semiconductor device further includes a field stop region in the semiconductor body between the drift region and the second main surface. The field stop region includes a plurality of impurity peaks. A first impurity peak of the plurality of impurity peaks has a larger concentration than a second impurity peak of the plurality of impurity peaks. The first impurity peak includes hydrogen and the second impurity peak includes helium.

公开(公告)号：US20190189463A1

公开(公告)日：2019-06-20

申请号：US16222592

申请日：2018-12-17

Applicant: Infineon Technologies AG

Inventor： Gerhard Schmidt ,  Mario Barusic ,  Benedikt Stoib

IPC: H01L21/322 ,  H01L27/06 ,  H01L29/32 ,  H01L29/66 ,  H01L29/739 ,  H01L29/861 ,  H01L49/02

CPC classification number: H01L21/3223 ,  H01L27/0664 ,  H01L28/10 ,  H01L29/32 ,  H01L29/66136 ,  H01L29/66333 ,  H01L29/7395 ,  H01L29/861

Abstract: A method for forming a semiconductor device includes incorporating recombination center atoms into a semiconductor substrate. The method further includes, after incorporating the recombination center atoms into the semiconductor substrate, implanting noble gas atoms into a doping region of a diode structure and/or a transistor structure, the doping region being arranged at a surface of the semiconductor substrate.

公开(公告)号：US20190172934A1

公开(公告)日：2019-06-06

申请号：US16269045

申请日：2019-02-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Kwang-won LEE ,  Hye-min KANG ,  Jae-gil LEE

IPC: H01L29/739 ,  H01L29/06 ,  H01L21/225 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/36 ,  H01L29/10

CPC classification number: H01L29/7395 ,  H01L21/2253 ,  H01L21/266 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/404 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7811

Abstract: In at least one general aspect, a method can include forming a plurality of first active pillars and a plurality of edge pillars in a first semiconductor layer including an active region and a termination region, and forming a second semiconductor layer on the first semiconductor layer. The method can include forming a plurality of second active pillars and a plurality of preliminary charge balance layers in the second semiconductor layer, and annealing the first and second semiconductor layers such that the plurality of first active pillars and the plurality of second active pillars are connected by diffusing impurities implanted into the plurality of first active pillars and the plurality of second active pillars.