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公开(公告)号：US20240147736A1
公开(公告)日：2024-05-02
申请号：US17974028
申请日：2022-10-26
CPC分类号： H01L27/2445 , H01L23/481 , H01L45/1206 , H01L45/1253 , H01L45/16
摘要： Structures that include resistive memory elements and methods of forming a structure that includes resistive memory elements. The structure comprises a bipolar junction transistor including a base, a first terminal having a first raised semiconductor layer over the base, and a second terminal having a second raised semiconductor layer over the base. The first raised semiconductor layer is spaced in a lateral direction from the second raised semiconductor layer. The structure further comprises a resistive memory element including a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. The first electrode of the resistive memory element is coupled to the first terminal of the bipolar junction transistor.
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公开(公告)号：US20180308547A1
公开(公告)日：2018-10-25
申请号：US16017806
申请日：2018-06-25
发明人： Jeffrey LILLE , Luiz M. FRANCA-NETO
CPC分类号： G11C13/0069 , G11C11/5678 , G11C13/0002 , G11C13/0004 , G11C2013/0092 , G11C2213/51 , H01L27/2436 , H01L27/2445 , H01L45/06 , H01L45/065 , H01L45/1233 , H01L45/1246 , H01L45/126 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/148
摘要： Embodiments of the present disclosure generally relate to electronic devices, and more specifically, to multi-level phase change devices. In one embodiment, a memory cell device is provided. The memory cell device generally includes a top surface, a bottom surface and a cell body between the top surface and the bottom surface. The cell body may include a plurality of phase change material layers, which may be used to store data of the cell. In another embodiment, a method of programming a memory cell is provided. The method generally may include applying a sequence of different pulses to each phase change material layer of the cell as the voltage of each pulse in the sequence is ratcheted down from the start of a write cycle to the end of a write cycle.
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公开(公告)号：US10084016B2
公开(公告)日：2018-09-25
申请号：US14086460
申请日：2013-11-21
CPC分类号： H01L27/2463 , H01L27/2427 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.
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公开(公告)号：US09990994B2
公开(公告)日：2018-06-05
申请号：US15854916
申请日：2017-12-27
发明人： Andrea Redaelli
CPC分类号： G11C13/0069 , G11C7/04 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C2013/008 , G11C2013/0088 , H01L27/2445 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/144
摘要： Methods for programming data to an array of memory cells having a first memory cell, a second memory cell that is adjacent to the first memory cell in a first direction along a first axis, and a third memory cell that is adjacent to the first memory cell in a second direction along a second axis.
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公开(公告)号：US20180122473A1
公开(公告)日：2018-05-03
申请号：US15854916
申请日：2017-12-27
发明人： Andrea Redaelli
CPC分类号： G11C13/0069 , G11C7/04 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C2013/008 , G11C2013/0088 , H01L27/2445 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/144
摘要： Methods for programming data to an array of memory cells having a first memory cell, a second memory cell that is adjacent to the first memory cell in a first direction along a first axis, and a third memory cell that is adjacent to the first memory cell in a second direction along a second axis.
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公开(公告)号：US20180114813A1
公开(公告)日：2018-04-26
申请号：US15851422
申请日：2017-12-21
IPC分类号： H01L27/24 , H01L45/00 , H01L29/66 , H01L21/762 , H01L27/102 , H01L29/732 , H01L29/423 , H01L29/417 , H01L29/06 , H01L21/033
CPC分类号： H01L27/2463 , H01L21/0338 , H01L21/76224 , H01L27/1022 , H01L27/2445 , H01L29/0649 , H01L29/41708 , H01L29/42304 , H01L29/66272 , H01L29/732 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A method and resulting structure, is disclosed to fabricate vertical bipolar junction transistors including a regular array of base contact pillars and emitter contact pillars with a at least one dimension below the minimum lithographical resolution, F, of the lithographic technique employed. A storage element, such as a phase change storage element, can be formed above the regular array of base contact pillars and emitter contact pillars.
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公开(公告)号：US20170243923A1
公开(公告)日：2017-08-24
申请号：US15288233
申请日：2016-10-07
发明人： Ji-hyun JEONG , Gwan-hyeob KOH , Dae-hwan KANG
CPC分类号： H01L27/2481 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C2213/71 , G11C2213/72 , H01L27/1026 , H01L27/2427 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/144 , H01L45/16 , H01L45/1675
摘要： A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.
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公开(公告)号：US09735354B2
公开(公告)日：2017-08-15
申请号：US15153293
申请日：2016-05-12
IPC分类号： H01L45/00 , H01L27/24 , H01L23/525
CPC分类号： H01L45/06 , H01L23/5256 , H01L27/2445 , H01L27/2463 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1675 , H01L45/1683
摘要： A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.
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公开(公告)号：US20170221965A1
公开(公告)日：2017-08-03
申请号：US15487743
申请日：2017-04-14
发明人： Ugo Russo , Andrea Redaelli , Giorgio Servalli
CPC分类号： H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/144 , H01L45/16 , H01L45/1608
摘要： Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. Additional phase change memory apparatuses include dummy columns positioned between memory columns and base contact columns. The dummy columns include phase change memory cells and lack heating elements coupled to the phase change memory cells thereof. Additional phase change memory apparatuses include heating elements operably coupled to phase change memory cells. An interfacial area between the heating elements and the phase change memory cells has a length that is independent of a bit line width. Methods relate to forming such phase change memory apparatuses.
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公开(公告)号：US20170117326A1
公开(公告)日：2017-04-27
申请号：US15398228
申请日：2017-01-04
IPC分类号： H01L27/24 , H01L29/66 , H01L45/00 , H01L29/732
CPC分类号： H01L27/2445 , H01L27/226 , H01L29/0821 , H01L29/66272 , H01L29/732 , H01L45/04 , H01L45/06 , H01L45/16
摘要： The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer.
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