公开(公告)号：US20190252611A1

公开(公告)日：2019-08-15

申请号：US16226708

申请日：2018-12-20

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Christelle CHARPIN-NICOLLE ,  Remy Gassilloud ,  Alain Persico

IPC: H01L45/00 ,  G11C11/56

CPC classification number: H01L45/1608 ,  G11C11/56 ,  H01L21/76877 ,  H01L45/08 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1683

Abstract: The present invention relates to a method for producing a via through a base layer of a microelectronic device, the method including formation of a hole leading to at least one first face of the base layer and filling the hole by at least one first filling material. The method also includes at least partially removing the at least one first filling material over a depth from the first face of the base layer, the depth being strictly less than a thickness dimension of the hole, so as to produce a hollow portion. Further, method includes a second step of at least partially filling the hollow portion by at least one second filling material.

公开(公告)号：US20190067571A1

公开(公告)日：2019-02-28

申请号：US15687038

申请日：2017-08-25

Applicant: Micron Technology, Inc.

Inventor： Lorenzo Fratin ,  Fabio Pellizzer

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1246 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/1683

Abstract: A self-selecting memory cell may be composed of a memory material that changes threshold voltages based on the polarity of the voltage applied across it. Such a memory cell may be formed at the intersection of a conductive pillar and electrode plane in a memory array. A dielectric material may be formed between the memory material of the memory cell and the corresponding electrode plane. The dielectric material may form a barrier that prevents harmful interactions between the memory material and the material that makes up the electrode plane. In some cases, the dielectric material may also be positioned between the memory material and the conductive pillar to form a second dielectric barrier. The second dielectric barrier may increase the symmetry of the memory array or prevent harmful interactions between the memory material and an electrode cylinder or between the memory material and the conductive pillar.

公开(公告)号：US20180375024A1

公开(公告)日：2018-12-27

申请号：US15939832

申请日：2018-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ting Chu ,  Tong-Chern Ong ,  Ying-Lang Wang

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1246 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

Abstract: The present disclosure relates to an RRAM device having an electrode with an oxygen barrier structure, which is configured to improve RRAM reliability by mitigating oxygen movement and thereby maintaining oxygen within close proximity of a dielectric data storage layer, and an associated method of formation. In some embodiments, the RRAM device has a bottom electrode disposed over a lower interconnect layer surrounded by a ILD layer. A dielectric data storage layer having a variable resistance is located above the bottom electrode, and a multi-layer top electrode disposed over the dielectric data storage layer. The multi-layer top electrode has conductive top electrode layers separated by an oxygen barrier structure configured to mitigate movement of oxygen within the multi-layer top electrode. By including an oxygen barrier structure within the top electrode, the reliability of the RRAM device is improved since oxygen is kept close to the dielectric data storage layer.

公开(公告)号：US20180351097A1

公开(公告)日：2018-12-06

申请号：US16039769

申请日：2018-07-19

Applicant: Micron Technology, Inc.

Inventor： Swapnil A. Lengade ,  John M. Meldrim ,  Andrea Gotti

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1608 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/144

Abstract: Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, and a second electrode portion is coupled to the second chalcogenide structure. An electrically conductive barrier material is disposed between the first and second electrode portions.

公开(公告)号：US20180351093A1

公开(公告)日：2018-12-06

申请号：US15611029

申请日：2017-06-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ming-Che WU ,  Alvaro PADILLA ,  Tanmay KUMAR

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC classification number: H01L45/1246 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  H01L27/2454 ,  H01L27/2463 ,  H01L27/249 ,  H01L45/08 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1641

Abstract: A resistive memory device, such as a BMC ReRAM device, includes at least one resistive memory element which contains a carbon barrier material portion and a resistive memory material portion that is disposed between a first electrode and a second electrode.

公开(公告)号：US20180331285A1

公开(公告)日：2018-11-15

申请号：US16040515

申请日：2018-07-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Swapnil A. Lengade ,  John M. Meldrim ,  Andrea Gotti

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1608 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/144

Abstract: Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, a second electrode portion is coupled to the second chalcogenide structure, and a third electrode portion is between the first and second electrode portions. A first portion of an electrically conductive barrier material is disposed between the first and third electrode portions. A second portion of the electrically conductive barrier material is disposed between the second and third electrode portions.

公开(公告)号：US20180254414A1

公开(公告)日：2018-09-06

申请号：US15878036

申请日：2018-01-23

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Sophie BERNASCONI ,  Christelle Charpin-Nicolle ,  Aomar Halimaoui

IPC: H01L45/00 ,  G11C13/00

CPC classification number: H01L45/10 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/56 ,  H01L21/02258 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1641

Abstract: The present invention relates to a memory device comprising a first electrode (27), a second electrode (28) and an active portion that can change conductive state, positioned between a first face of the first electrode (27) and a first face of the second electrode (28).The first electrode (27) comprises an upper portion forming the first face of the first electrode (27). At least one out of the upper portion and the active portion that can change conductive state comprises a porous layer (15).

公开(公告)号：US20180205011A1

公开(公告)日：2018-07-19

申请号：US15405555

申请日：2017-01-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kevin W. Brew ,  Talia S. Gershon ,  Dennis M. Newns ,  Saurabh Singh

IPC: H01L45/00

CPC classification number: H01L45/085 ,  G06N3/063 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1641

Abstract: Embodiments are directed to a memristive device. The memristive device includes a first conductive material layer. An oxide material layer is arranged on the first conductive layer. And a second conductive material layer is arranged on the oxide material layer, wherein the second conductive material layer comprises a metal-alkali alloy.

公开(公告)号：US20180198064A1

公开(公告)日：2018-07-12

申请号：US15863199

申请日：2018-01-05

Applicant: Intermolecular, Inc.

Inventor： Tony Chiang ,  Sergey V Barabash ,  Karl Littau ,  Vijay Kris Narasimhan ,  Stephen Weeks

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1233 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1608

Abstract: Provided are novel compositions of current compliance layers (CCLs) as well as novel methods of fabricating such CCLs and novel architectures of arranging CCLs and memory cells in memory arrays. A CCL may comprise one of sulfur (S), selenium (Se), and tellurium (Te). The CCL may further comprise one of germanium (Ge) and silicon (Si). CCLs may be fabricated as amorphous structure and remain amorphous when heated to 400° C. or 450° C. and above. In some embodiments, CCLs have crystallization temperatures of greater than 400° C. and, in some embodiments, glass transition temperatures of greater than 400° C. CCLs may be fabricated using atomic layer deposition (ALD) as a nanolaminate of layers having different compositions. The composition, number, and arrangement of the layers in the nanolaminate is specifically selected to yield a desired composition of CCL.

公开(公告)号：US10003019B2

公开(公告)日：2018-06-19

申请号：US15344226

申请日：2016-11-04

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation

Inventor： Jia Xu ,  Jiadong Ren

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1625 ,  H01L45/1675

Abstract: A method for manufacturing a semiconductor device may include the following steps: preparing a substrate; preparing a first insulating layer on the substrate; preparing an electrode in the first insulating layer; preparing a second insulating layer on the first insulating layer; removing (e.g., using a dry etching process or a wet etching process) a portion of the second insulating layer to form a hole that at least partially exposes the electrode; providing a phase change material layer that may cover the electrode; and removing (e.g., using a sputtering process such as an argon sputtering process), a portion of the phase change material layer positioned inside the hole to form a phase change member that may expose a first portion of (a top side of) the electrode and may directly contact a second portion of (the top side of) the electrode.