公开(公告)号：US12156409B2

公开(公告)日：2024-11-26

申请号：US16934166

申请日：2020-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yang Chang ,  Wen-Ting Chu

IPC: H10B63/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10N70/00

Abstract: Various embodiments of the present application are directed a memory layout for reduced line loading. In some embodiments, a memory device comprises an array of bit cells, a first conductive line, a second conductive line, and a plurality of conductive bridges. The first and second conductive lines may, for example, be source lines or some other conductive lines. The array of bit cells comprises a plurality of rows and a plurality of columns, and the plurality of columns comprise a first column and a second column. The first conductive line extends along the first column and is electrically coupled to bit cells in the first column. The second conductive line extends along the second column and is electrically coupled to bit cells in the second column. The conductive bridges extend from the first conductive line to the second conductive line and electrically couple the first and second conductive lines together.

公开(公告)号：US11678494B2

公开(公告)日：2023-06-13

申请号：US16934192

申请日：2020-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yang Chang ,  Wen-Ting Chu

IPC: H01L21/768 ,  H01L27/24 ,  H01L23/528 ,  H01L23/522 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L21/7684 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5221 ,  H01L45/16

Abstract: Various embodiments of the present application are directed a memory layout for reduced line loading. In some embodiments, a memory device comprises an array of bit cells, a first conductive line, a second conductive line, and a plurality of conductive bridges. The first and second conductive lines may, for example, be source lines or some other conductive lines. The array of bit cells comprises a plurality of rows and a plurality of columns, and the plurality of columns comprise a first column and a second column. The first conductive line extends along the first column and is electrically coupled to bit cells in the first column. The second conductive line extends along the second column and is electrically coupled to bit cells in the second column. The conductive bridges extend from the first conductive line to the second conductive line and electrically couple the first and second conductive lines together.

公开(公告)号：US20230113903A1

公开(公告)日：2023-04-13

申请号：US18080696

申请日：2022-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Der CHIH ,  Chung-Cheng Chou ,  Wen-Ting Chu

IPC: G11C13/00

Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

公开(公告)号：US11557344B2

公开(公告)日：2023-01-17

申请号：US17330248

申请日：2021-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Der Chih ,  Chung-Cheng Chou ,  Wen-Ting Chu

IPC: G11C11/00 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

公开(公告)号：US11257844B2

公开(公告)日：2022-02-22

申请号：US16569487

申请日：2019-09-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tzu-Yu Chen ,  Sheng-Hung Shih ,  Kuo-Chi Tu ,  Wen-Ting Chu

IPC: H01L27/1159 ,  H01L23/522

Abstract: A semiconductor device includes a lower intermetal dielectric (IMD) layer, a middle conductive line, and a ferroelectric random access memory (FRAM) structure. The middle conductive line is embedded in the lower IMD layer. The FRAM structure is over the lower IMD layer and the middle conductive line. The FRAM structure includes a bottom electrode, a ferroelectric layer, and a top electrode. The bottom electrode is over the middle conductive line and in contact with the lower IMD layer. The ferroelectric layer is over the bottom electrode. The top electrode is over the ferroelectric layer.

公开(公告)号：US11004975B2

公开(公告)日：2021-05-11

申请号：US16940335

申请日：2020-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Chi Tu ,  Jen-Sheng Yang ,  Sheng-Hung Shih ,  Tong-Chern Ong ,  Wen-Ting Chu

IPC: H01L29/78 ,  H01L29/51 ,  G11C11/22 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/66

Abstract: A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.

公开(公告)号：US20210111339A1

公开(公告)日：2021-04-15

申请号：US16601800

申请日：2019-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh-Fei Chiu ,  Wen-Ting Chu ,  Yong-Shiuan Tsair ,  Yu-Wen Liao ,  Chin-Yu Mei ,  Po-Hao Tseng

IPC: H01L45/00 ,  H01L23/48 ,  H01L23/495 ,  H01L23/31

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower inter-level dielectric (ILD) structure surrounding a plurality of lower interconnect layers over a substrate. An etch stop material is disposed over the lower ILD structure. A bottom electrode is arranged over an upper surface of the etch stop material, a data storage structure is disposed on an upper surface of the bottom electrode and is configured to store a data state, and a top electrode is disposed on an upper surface of the data storage structure. A first interconnect via contacts the upper surface the bottom electrode and a second interconnect via contacts the top electrode.

公开(公告)号：US10930333B2

公开(公告)日：2021-02-23

申请号：US16267668

申请日：2019-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yong-Shiuan Tsair

IPC: H01L21/00 ,  G11C11/22 ,  H01L27/11592 ,  H01L27/1159 ,  H01L29/51

Abstract: In some embodiments, the present disclosure relates to a memory structure. The memory structure has a source region and a drain region disposed within a substrate. A select gate disposed over the substrate between the source region and the drain region. A ferroelectric random access memory (FeRAM) device is disposed over the substrate between the select gate and the source region. The FeRAM device includes a ferroelectric material arranged between the substrate and a conductive electrode.

公开(公告)号：US20210035992A1

公开(公告)日：2021-02-04

申请号：US16663952

申请日：2019-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Wen-Ting Chu ,  Chih-Hsiang Chang ,  Fu-Chen Chang

IPC: H01L27/11502

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a lower dielectric structure over a substrate. A lower insulating structure is over the lower dielectric structure and has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure. The upper surface of the lower insulating structure extends past outermost sidewalls of the bottom electrode. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The bottom electrode has interior sidewalls coupled to a horizontally extending surface to define a recess within an upper surface of the bottom electrode. The horizontally extending surface is below the upper surface of the lower insulating structure.

公开(公告)号：US10796759B2

公开(公告)日：2020-10-06

申请号：US16413937

申请日：2019-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Chieh Yang ,  Chih-Yang Chang ,  Chang-Sheng Liao ,  Hsia-Wei Chen ,  Jen-Sheng Yang ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Wen-Ting Chu ,  Manish Kumar Singh ,  Chi-Tsai Chen

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/16

Abstract: The present disclosure, in some embodiments, relates to a method of operating a resistive random access memory (RRAM) array. The method includes applying a word-line voltage to a selected word-line during a read operation. A non-zero voltage is applied to a selected bit-line during the read operation. A first voltage is applied to a selected source-line during the read operation. The first voltage is smaller than a second voltage applied to an unselected source-line during the read operation.