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公开(公告)号：US10311952B2
公开(公告)日：2019-06-04
申请号：US15937257
申请日：2018-03-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Chieh Yang , Chih-Yang Chang , Chang-Sheng Liao , Hsia-Wei Chen , Jen-Sheng Yang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Manish Kumar Singh , Chi-Tsai Chen
Abstract: In some embodiments, the present disclosure relates to a resistive random access memory (RRAM) memory circuit. The memory circuit has a word-line decoder operably coupled to a first RRAM device and a second RRAM device by a word-line. A bit-line decoder is coupled to the first RRAM device by a first bit-line and to the second RRAM device by a second bit-line. A bias element is configured to apply a first non-zero bias voltage to the second bit-line concurrent to the bit-line decoder applying a non-zero voltage to the first bit-line.
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公开(公告)号：US20180218770A1
公开(公告)日：2018-08-02
申请号：US15937257
申请日：2018-03-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Chieh Yang , Chih-Yang Chang , Chang-Sheng Liao , Hsia-Wei Chen , Jen-Sheng Yang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Manish Kumar Singh , Chi-Tsai Chen
CPC classification number: G11C13/004 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C2213/79 , G11C2213/82
Abstract: In some embodiments, the present disclosure relates to a resistive random access memory (RRAM) memory circuit. The memory circuit has a word-line decoder operably coupled to a first RRAM device and a second RRAM device by a word-line. A bit-line decoder is coupled to the first RRAM device by a first bit-line and to the second RRAM device by a second bit-line. A bias element is configured to apply a first non-zero bias voltage to the second bit-line concurrent to the bit-line decoder applying a non-zero voltage to the first bit-line.
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公开(公告)号：US20170236581A1
公开(公告)日：2017-08-17
申请号：US15425213
申请日：2017-02-06
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Chieh Yang , Chih-Yang Chang , Chang-Sheng Liao , Hsia-Wei Chen , Jen-Sheng Yang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Manish Kumar Singh , Chi-Tsai Chen
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C2213/79 , G11C2213/82
Abstract: The present disclosure relates to a method and apparatus for performing a read operation of an RRAM cell, which applies a non-zero bias voltage to unselected bit-lines and select-lines to increase a read current window without damaging corresponding access transistors. In some embodiments, the method may be performed by activating a word-line coupled to a row of RRAM cells comprising a selected RRAM device by applying a first read voltage to the word-line. A second read voltage is applied to a bit-line coupled to a first electrode of the selected RRAM device. One or more non-zero bias voltages are applied to bit-lines and select-lines coupled to RRAM cells, within the row of RRAM cells, having unselected RRAM devices.
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公开(公告)号：US10796759B2
公开(公告)日：2020-10-06
申请号：US16413937
申请日：2019-05-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Chieh Yang , Chih-Yang Chang , Chang-Sheng Liao , Hsia-Wei Chen , Jen-Sheng Yang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Manish Kumar Singh , Chi-Tsai Chen
Abstract: The present disclosure, in some embodiments, relates to a method of operating a resistive random access memory (RRAM) array. The method includes applying a word-line voltage to a selected word-line during a read operation. A non-zero voltage is applied to a selected bit-line during the read operation. A first voltage is applied to a selected source-line during the read operation. The first voltage is smaller than a second voltage applied to an unselected source-line during the read operation.
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公开(公告)号：US10283384B2
公开(公告)日：2019-05-07
申请号：US14696973
申请日：2015-04-27
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Manish Kumar Singh , Bo-Wei Chou , Jui-Ming Shih , Wen-Yu Ku , Ping-Jung Huang , Pi-Chun Yu
IPC: H01L21/67 , H01L21/311
Abstract: A method for etching an etch layer formed on a front side of a wafer and a wafer etching apparatus are provided. The wafer etching apparatus includes a first flow channel, a temperature-regulating module, and a second flow channel. The first flow channel is configured to carry a preheated/precooled liquid for controlling a temperature of a wafer. The temperature-regulating module is coupled to the first flow channel. The temperature-regulating module is configured to control a temperature of the liquid in the first flow channel. The second flow channel is configured to carry an etchant for etching an etch layer formed on a front side of the wafer. The method includes: controlling the temperature of the wafer by using the preheated/precooled liquid; and etching the etch layer with the etchant.
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Patent Agency Ranking
公开(公告)号：US09934853B2
公开(公告)日：2018-04-03
申请号：US15425213
申请日：2017-02-06
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Chieh Yang , Chih-Yang Chang , Chang-Sheng Liao , Hsia-Wei Chen , Jen-Sheng Yang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Manish Kumar Singh , Chi-Tsai Chen
CPC classification number: G11C13/004 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C2213/79 , G11C2213/82
Abstract: The present disclosure relates to a method and apparatus for performing a read operation of an RRAM cell, which applies a non-zero bias voltage to unselected bit-lines and select-lines to increase a read current window without damaging corresponding access transistors. In some embodiments, the method may be performed by activating a word-line coupled to a row of RRAM cells comprising a selected RRAM device by applying a first read voltage to the word-line. A second read voltage is applied to a bit-line coupled to a first electrode of the selected RRAM device. One or more non-zero bias voltages are applied to bit-lines and select-lines coupled to RRAM cells, within the row of RRAM cells, having unselected RRAM devices.
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公开(公告)号：US09553265B1
公开(公告)日：2017-01-24
申请号：US14995294
申请日：2016-01-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jen-Sheng Yang , Chih-Yang Chang , Chin-Chieh Yang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Yu-Wen Liao , Manish Kumar Singh
CPC classification number: H01L45/1253 , H01L27/2436 , H01L45/08 , H01L45/122 , H01L45/146 , H01L45/1666 , H01L45/1691
Abstract: The present disclosure relates to an integrated circuit, which includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a lower metal layer, an intermediate metal layer disposed over the lower metal layer, and an upper metal layer disposed over the intermediate metal layer. An upper surface of the lower metal layer and a lower surface of the intermediate metal layer are spaced vertically apart by a first distance. A resistive random access memory (RRAM) cell is arranged between the lower metal layer and the upper metal layer. The RRAM cell includes a bottom electrode and a top electrode which are separated by a data storage layer having a variable resistance. The data storage layer vertically spans a second distance that is greater than the first distance.
Abstract translation: 本公开涉及集成电路，其包括设置在半导体衬底上的半导体衬底和互连结构。 互连结构包括下金属层，设置在下金属层上的中间金属层和设置在中间金属层上的上金属层。 下金属层的上表面和中间金属层的下表面间隔开第一距离。 电阻随机存取存储器（RRAM）单元布置在下金属层和上金属层之间。 RRAM单元包括由具有可变电阻的数据存储层分离的底部电极和顶部电极。 数据存储层垂直地跨越大于第一距离的第二距离。
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公开(公告)号：US11784065B2
公开(公告)日：2023-10-10
申请号：US16404533
申请日：2019-05-06
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Manish Kumar Singh , Bo-Wei Chou , Jui-Ming Shih , Wen-Yu Ku , Ping-Jung Huang , Pi-Chun Yu
IPC: H01L21/67 , H01L21/311
CPC classification number: H01L21/6708 , H01L21/67086 , H01L21/67109 , H01L21/67248 , H01L21/31111
Abstract: A method includes rotating a wafer, dispensing a liquid from a center of the wafer to an edge of the wafer to control a temperature of the wafer, and etching an etch layer of the wafer with an etchant during or after dispensing the liquid. The liquid is dispensed through a nozzle.
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公开(公告)号：US20190272873A1
公开(公告)日：2019-09-05
申请号：US16413937
申请日：2019-05-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Chieh Yang , Chih-Yang Chang , Chang-Sheng Liao , Hsia-Wei Chen , Jen-Sheng Yang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Manish Kumar Singh , Chi-Tsai Chen
Abstract: The present disclosure, in some embodiments, relates to a method of operating a resistive random access memory (RRAM) array. The method includes applying a word-line voltage to a selected word-line during a read operation. A non-zero voltage is applied to a selected bit-line during the read operation. A first voltage is applied to a selected source-line during the read operation. The first voltage is smaller than a second voltage applied to an unselected source-line during the read operation.
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公开(公告)号：US09941470B2
公开(公告)日：2018-04-10
申请号：US15403399
申请日：2017-01-11
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jen-Sheng Yang , Chih-Yang Chang , Chin-Chieh Yang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Yu-Wen Liao , Manish Kumar Singh
CPC classification number: H01L45/1253 , H01L27/2436 , H01L45/08 , H01L45/122 , H01L45/146 , H01L45/1666 , H01L45/1691
Abstract: The present disclosure relates to an integrated circuit, which includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a lower metal layer, an intermediate metal layer disposed over the lower metal layer, and an upper metal layer disposed over the intermediate metal layer. An upper surface of the lower metal layer and a lower surface of the intermediate metal layer are spaced vertically apart by a first distance. A resistive random access memory (RRAM) cell is arranged between the lower metal layer and the upper metal layer. The RRAM cell includes a bottom electrode and a top electrode which are separated by a data storage layer having a variable resistance. The data storage layer vertically spans a second distance that is greater than the first distance.
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