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公开(公告)号：US20190214560A1
公开(公告)日：2019-07-11
申请号：US16352443
申请日：2019-03-13
Applicant: International Business Machines Corporation
Inventor： Matthew J. BrightSky
CPC classification number: H01L45/1683 , H01L27/2409 , H01L27/2427 , H01L27/2463 , H01L27/2481 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/1233 , H01L45/124 , H01L45/1246 , H01L45/144 , H01L45/1608 , H01L45/1616 , H01L45/1666
Abstract: An illustrative method of fabricating a memory array structure includes: forming at least one access device layer on an upper surface of a first conductive layer, the access device layer being in electrical connection with the first conductive layer; forming a sacrificial layer on an upper surface of the access device layer; etching the access device layer and the sacrificial layer using a same masking feature to form an access device that is self-aligned with a portion of the sacrificial layer; replacing a portion of the sacrificial layer with memory storage material to form a storage element, a first terminal of the storage element being in electrical connection with the access device; and forming a second conductive layer on an upper surface of the storage element, a second terminal of the storage element being in electrical connection with the second conductive layer.
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2.发明申请公开(公告)号：US20190131522A1
公开(公告)日：2019-05-02
申请号：US16170056
申请日：2018-10-25
Applicant: Winbond Electronics Corp.
Inventor： Yu-Jen Lin , Yi-Chung Chen , Cheng-Jen Lai
IPC: H01L45/00
CPC classification number: H01L45/1253 , B24B1/00 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1666 , H01L45/1675
Abstract: A resistive memory, a manufacturing method thereof, and a chemical mechanical polishing process are provided. The resistive memory includes a first electrode, a variable resistance layer, and a second electrode. The first electrode is disposed on a substrate. The variable resistance layer is disposed on the first electrode. The second electrode is disposed on the variable resistance layer. The first electrode includes a first Ti layer, a Ti oxide layer, and a conductive layer sequentially disposed on the substrate.
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公开(公告)号：US20180277602A1
公开(公告)日：2018-09-27
申请号：US15987613
申请日：2018-05-23
Applicant: Micron Technology, Inc.
Inventor： Scott E. Sills , Durai Vishak Nirmal Ramaswamy
CPC classification number: H01L27/2436 , H01L27/2463 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/124 , H01L45/1253 , H01L45/141 , H01L45/145 , H01L45/16 , H01L45/1616 , H01L45/1666 , H01L45/1691
Abstract: A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. The covering material is removed over the spaced sense line contacts and the spaced sense line contacts are exposed. Access lines are formed. Sense lines are formed that are electrically coupled to the spaced sense line contacts. The sense lines are angled relative to the lines of spaced sense line contacts and relative to the access lines. Other embodiments, including structure independent of method, are disclosed.
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公开(公告)号：US20180190717A1
公开(公告)日：2018-07-05
申请号：US15653181
申请日：2017-07-18
Applicant: Micron Technology, Inc.
Inventor： Shigeru Sugioka
CPC classification number: H01L27/2472 , G11C11/161 , G11C11/1673 , G11C11/1675 , H01L27/228 , H01L27/2436 , H01L43/12 , H01L45/06 , H01L45/085 , H01L45/1253 , H01L45/16 , H01L45/1666
Abstract: Memory devices include an array of memory cells including magnetic tunnel junction regions. The array of memory cells includes access lines extending in a first direction and data lines extending in a second direction transverse to the first direction. A common source electrically couples memory cells of the array in both the first direction and the second direction. Electronic systems include such a memory device electrically coupled to a processor, to which at least one input device and at least one output device is electrically coupled. Methods of forming such an array of memory cells including a common source.
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公开(公告)号：US20180019390A1
公开(公告)日：2018-01-18
申请号：US15715413
申请日：2017-09-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsia-Wei Chen , Wen-Ting Chu , Kuo-Chi Tu , Chih-Yang Chang , Chin-Chieh Yang , Yu-Wen Liao , Wen-Chun You , Sheng-Hung Shih
CPC classification number: H01L45/1233 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/12 , H01L45/122 , H01L45/124 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1666 , H01L45/1683
Abstract: Some embodiments relate to an integrated circuit device, which includes a bottom electrode, a dielectric layer, and top electrode. The dielectric layer is disposed over the bottom electrode. The top electrode is disposed over the dielectric layer, and an upper surface of the top electrode exhibits a recess. A via is disposed over the top electrode. The via makes electrical contact with only a tapered sidewall of the recess without contacting a bottom surface of the recess.
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Patent Agency Ranking
公开(公告)号：US20170317275A1
公开(公告)日：2017-11-02
申请号：US15654405
申请日：2017-07-19
Inventor： Philippe Boivin , Simon Jeannot
CPC classification number: H01L45/06 , G11C13/0004 , G11C2213/79 , G11C2213/82 , H01L27/2436 , H01L27/2463 , H01L45/1206 , H01L45/1226 , H01L45/1233 , H01L45/124 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1666
Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
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公开(公告)号：US09793321B2
公开(公告)日：2017-10-17
申请号：US14970347
申请日：2015-12-15
Inventor： Philippe Boivin , Simon Jeannot
CPC classification number: H01L27/2436 , G11C13/0004 , G11C2213/79 , G11C2213/82 , H01L27/2463 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/146 , H01L45/147 , H01L45/1666
Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.
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公开(公告)号：US09666796B2
公开(公告)日：2017-05-30
申请号：US15252746
申请日：2016-08-31
Applicant: Tsinghua University , HON HAI PRECISION INDUSTRY CO., LTD.
Inventor： Peng Liu , Yang Wu , Qun-Qing Li , Kai-Li Jiang , Jia-Ping Wang , Shou-Shan Fan
IPC: H01L45/00
CPC classification number: H01L45/06 , H01L45/1206 , H01L45/1226 , H01L45/126 , H01L45/144 , H01L45/1608 , H01L45/1666
Abstract: A method for making phase change memory cell includes following steps. A carbon nanotube wire is located on a surface of the substrate, wherein the carbon nanotube wire includes a first end and a second end opposite to the first end. A bending portion is formed by bending the carbon nanotube wire. A first electrode, a second electrode, and a third electrode are applied on the surface of the substrate, wherein the first electrode is electrically connected to the first end, the second electrode is electrically connected to the second end, and the third end is spaced from the bending portion of the carbon nanotube wire. A phase change layer is deposited to cover the bending structure and electrically connects to the third electrode.
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公开(公告)号：US20170133435A1
公开(公告)日：2017-05-11
申请号：US15412566
申请日：2017-01-23
Applicant: HGST, Inc.
Inventor： Daniel Robert SHEPARD
CPC classification number: H01L27/2481 , H01L27/2427 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/141 , H01L45/145 , H01L45/1608 , H01L45/1666 , H01L45/1683
Abstract: A method for fabricating 3-D cross-point memory arrays, and more particularly to fabricating phase change memory (PCM) and resistive RAM (ReRAM or RRAM) 3-D memory arrays having a cell size footprint of 4F2. The method for forming a plurality of layers of memory cells using a limited number of photolithographic patterning steps is applicable to memory devices having single or multiple storage bits per cell, such as cells having anywhere from one to eight bits per cell or more. These bits are stacked three dimensionally and include memory cells based on phase change material, on resistive change material, on magnetic field alignment, on mechanical switching, and on other memory cells based on other information storage technologies.
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公开(公告)号：US20160351803A1
公开(公告)日：2016-12-01
申请号：US15237387
申请日：2016-08-15
Inventor： Fu-Ting Sung , Ching-Pei Hsieh , Chia-Shiung Tsai , Chern-Yow Hsu , Shih-Chang Liu
IPC: H01L45/00
CPC classification number: H01L45/1253 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1246 , H01L45/146 , H01L45/16 , H01L45/1608 , H01L45/1666 , H01L45/1683
Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.
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