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公开(公告)号：US20240023460A1
公开(公告)日：2024-01-18
申请号：US18360510
申请日：2023-07-27
摘要： The present disclosure provides a semiconductor structure, including an Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M)th metal layer over the Nth metal layer. N and M are positive integers. The (N+M)th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.
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公开(公告)号：US20230363285A1
公开(公告)日：2023-11-09
申请号：US18353254
申请日：2023-07-17
发明人： Min-Yung Ko , Chern-Yow Hsu , Chang-Ming Wu , Shih-Chang Liu
CPC分类号： H10N50/01 , H10B61/22 , H10B63/30 , H10N50/10 , H10N50/80 , H10N70/021 , H10N70/063 , H10N70/068 , H10N70/841
摘要： Various embodiments of the present disclosure are directed towards a method for forming a memory cell. In some embodiments, a memory film is deposited over a substrate and comprises a bottom electrode layer, a top electrode layer, and a data storage film between the top and bottom electrode layers. A hard mask film is deposited over the memory film and comprises a conductive hard mask layer. The top electrode layer and the hard mask film are patterned to respectively form a top electrode and a hard mask over the top electrode. A trimming process is performed to decrease a sidewall angle between a sidewall of the hard mask and a bottom surface of the hard mask. An etch is performed into the data storage film with the hard mask in place after the trimming process to form a data storage structure underlying the top electrode.
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公开(公告)号：US20230361149A1
公开(公告)日：2023-11-09
申请号：US17882869
申请日：2022-08-08
发明人： Hsin-Hung Chen , Dun-Nian Yaung , Jen-Cheng Liu , Feng-Chi Hung , Wen-Chang Kuo , Hung-Wen Hsu , Shih-Chang Liu
IPC分类号： H01L27/146
CPC分类号： H01L27/14685 , H01L27/1463 , H01L27/14641 , H01L27/14643
摘要： In some embodiments, the present disclosure relates to a method for forming an image sensor and associated device structure. A backside deep trench isolation (BDTI) structure is formed in a substrate separating a plurality of pixel regions. The BDTI structure encloses a plurality of photodiodes and comprising a first BDTI component arranged at a crossroad of the plurality of pixel regions and a second BDTI component arranged at remaining peripheries of the plurality of pixel regions. The first BDTI component has a first depth from a backside of the substrate smaller than a second depth of the second BDTI component.
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公开(公告)号：US11665911B2
公开(公告)日：2023-05-30
申请号：US17389774
申请日：2021-07-30
发明人： Yuan-Tai Tseng , Chung-Chiang Min , Shih-Chang Liu
CPC分类号： H01L27/228 , H01L43/02 , H01L43/12
摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower interconnect disposed within a dielectric structure over a substrate. A memory device includes a data storage structure disposed between a bottom electrode and a top electrode. The bottom electrode is electrically coupled to the lower interconnect. A sidewall spacer includes an interior sidewall that continuously extends from along an outermost sidewall of the top electrode to below an outermost sidewall of the bottom electrode. The sidewall spacer further includes an outermost sidewall that extends from a bottom surface of the sidewall spacer to above a top of the bottom electrode.
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公开(公告)号：US11515473B2
公开(公告)日：2022-11-29
申请号：US16931632
申请日：2020-07-17
摘要： The present disclosure provides a semiconductor structure, including an Nth metal layer over a transistor region, where N is a natural number, and a bottom electrode over the Nth metal layer. The bottom electrode comprises a bottom portion having a first width, disposed in a bottom electrode via (BEVA), the first width being measured at a top surface of the BEVA, and an upper portion having a second width, disposed over the bottom portion. The semiconductor structure also includes a magnetic tunneling junction (MTJ) layer having a third width, disposed over the upper portion, a top electrode over the MTJ layer and an (N+1)th metal layer over the top electrode. The first width is greater than the third width.
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公开(公告)号：US10720571B2
公开(公告)日：2020-07-21
申请号：US16048247
申请日：2018-07-28
摘要： The present disclosure provides a semiconductor structure, including an Nth metal layer over a transistor region, where N is a natural number, and a bottom electrode over the Nth metal layer. The bottom electrode comprises a bottom portion having a first width, disposed in a bottom electrode via (BEVA), the first width being measured at a top surface of the BEVA, and an upper portion having a second width, disposed over the bottom portion. The semiconductor structure also includes a magnetic tunneling junction (MTJ) layer having a third width, disposed over the upper portion, a top electrode over the MTJ layer and an (N+1)th metal layer over the top electrode. The first width is greater than the third width.
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公开(公告)号：US10720568B2
公开(公告)日：2020-07-21
申请号：US16048457
申请日：2018-07-30
摘要： The present disclosure provides a semiconductor structure, including an Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M)th metal layer over the Nth metal layer. N and M are positive integers. The (N+M)th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.
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公开(公告)号：US10665600B2
公开(公告)日：2020-05-26
申请号：US15413256
申请日：2017-01-23
IPC分类号： H01L27/11568 , H01L29/792 , H01L29/423 , H01L21/311 , H01L29/66
摘要： A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.
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公开(公告)号：US10453932B2
公开(公告)日：2019-10-22
申请号：US15617691
申请日：2017-06-08
发明人： Ming Chyi Liu , Chang-Ming Wu , Shih-Chang Liu , Wei Cheng Wu , Harry-Hak-Lay Chuang , Chia-Shiung Tsai , Ru-Liang Lee
IPC分类号： H01L29/423 , H01L27/11521 , H01L29/66 , H01L21/28
摘要： An exemplary method includes forming a common source region in a substrate, and forming an isolation feature over the common source region. The common source region is disposed between the substrate and the isolation feature. The common source region and the isolation feature span a plurality of active regions of the substrate. A gate, such as an erase gate, may be formed after forming the common source region. In some implementations, the common source region is formed by etching the substrate to form a saw-tooth shaped recess region (or a U-shaped recess region) and performing an ion implantation process to form a doped region in a portion of the saw-tooth shaped recess region (or the U-shaped recess region), such that the common source region has a sawtooth profile (or a U-shaped profile).
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公开(公告)号：US10181558B2
公开(公告)日：2019-01-15
申请号：US15455720
申请日：2017-03-10
摘要： A magnetoresistive random access memory (MRAM) structure includes a bottom electrode structure. A magnetic tunnel junction (MTJ) element is over the bottom electrode structure. The MTJ element includes an anti-ferromagnetic material layer. A ferromagnetic pinned layer is over the anti-ferromagnetic material layer. A tunneling layer is over the ferromagnetic pinned layer. A ferromagnetic free layer is over the tunneling layer. The ferromagnetic free layer has a first portion and a demagnetized second portion. The MRAM also includes a top electrode structure over the first portion.
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