公开(公告)号：US12133469B2

公开(公告)日：2024-10-29

申请号：US17487049

申请日：2021-09-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tsung-Chieh Hsiao ,  Yu-Feng Yin ,  Liang-Wei Wang ,  Dian-Hau Chen

IPC: H10N50/01 ,  G11C11/16 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/01 ,  G11C11/161 ,  H10B61/22 ,  H10N50/80 ,  H10N50/85

Abstract: In a method of manufacturing a semiconductor device, a cell structure is formed. The cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack disposed on the bottom electrode and a hard mask layer disposed on the MTJ stack. A first insulating cover layer is formed over sidewall of the MTJ stack. A second insulating cover layer is formed over the first insulating cover layer and the hard mask layer. A first interlayer dielectric (ILD) layer is formed. The hard mask layer is exposed by etching the first ILD layer and the second insulating cover layer. A second ILD layer is formed. A contact opening is formed in the second ILD layer by patterning the second ILD layer and removing the hard mask layer. A conductive layer is formed in the contact opening so that the conductive layer contacts the MTJ stack.

公开(公告)号：US20240349515A1

公开(公告)日：2024-10-17

申请号：US18755693

申请日：2024-06-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Shu-Ru Wang ,  Yu-Tse Kuo ,  Chang-Hung Chen ,  Yi-Ting Wu ,  Shu-Wei Yeh ,  Ya-Lan Chiou ,  Chun-Hsien Huang

IPC: H10B61/00 ,  H10N50/80

CPC classification number: H10B61/22 ,  H10N50/80

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region and a second cell region and a diffusion region on the substrate extending through the first cell region and the second cell region. Preferably, the diffusion region includes a first H-shape and a second H-shape according to a top view.

公开(公告)号：US12120963B2

公开(公告)日：2024-10-15

申请号：US17484934

申请日：2021-09-24

Applicant: International Business Machines Corporation

Inventor： Lili Cheng ,  Ashim Dutta ,  Chih-Chao Yang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10N50/01 ,  H10B61/22

Abstract: A semiconductor structure comprises a bottom electrode contact, and a memory device comprising a bottom electrode disposed on the bottom electrode contact, at least one memory element layer disposed on the bottom electrode, and a top electrode disposed on the at least one memory element layer. A bit line contact is disposed on the top electrode and extends around sides of the memory device and of the bottom electrode contact. An encapsulation layer is disposed between the bit line contact and the sides of the memory device and of the bottom electrode contact.

公开(公告)号：US20240341102A1

公开(公告)日：2024-10-10

申请号：US18741721

申请日：2024-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： ALEXANDER KALNITSKY ,  HARRY-HAK-LAY CHUANG ,  SHENG-HAUNG HUANG ,  TIEN-WEI CHIANG

IPC: H10B61/00 ,  G01R33/09 ,  G11B5/39 ,  H10N50/01 ,  H10N50/10

CPC classification number: H10B61/22 ,  G01R33/098 ,  G11B5/3909 ,  H10N50/01 ,  H10N50/10 ,  G11C2211/5615

Abstract: The present disclosure provides a method for fabricating a semiconductor device. The method includes the operations below. A magnetic tunneling junction (MTJ) is formed on a substrate. A first dielectric layer is formed around the MTJ. A first metal interconnection is formed adjacent to the MTJ. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is removed to form an opening. A metal line is formed in the opening to electrically connect the MTJ and the first metal interconnection.

公开(公告)号：US12114576B2

公开(公告)日：2024-10-08

申请号：US18353254

申请日：2023-07-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Min-Yung Ko ,  Chern-Yow Hsu ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H10N50/01 ,  H10B61/00 ,  H10B63/00 ,  H10N50/10 ,  H10N50/80 ,  H10N70/00

CPC classification number: H10N50/01 ,  H10B61/22 ,  H10B63/30 ,  H10N50/10 ,  H10N50/80 ,  H10N70/021 ,  H10N70/063 ,  H10N70/068 ,  H10N70/841

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a memory cell. In some embodiments, a memory film is deposited over a substrate and comprises a bottom electrode layer, a top electrode layer, and a data storage film between the top and bottom electrode layers. A hard mask film is deposited over the memory film and comprises a conductive hard mask layer. The top electrode layer and the hard mask film are patterned to respectively form a top electrode and a hard mask over the top electrode. A trimming process is performed to decrease a sidewall angle between a sidewall of the hard mask and a bottom surface of the hard mask. An etch is performed into the data storage film with the hard mask in place after the trimming process to form a data storage structure underlying the top electrode.

公开(公告)号：US20240315144A1

公开(公告)日：2024-09-19

申请号：US18669572

申请日：2024-05-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： TSANN LIN ,  YA-LING LEE

IPC: H10N50/80 ,  H01F10/32 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  H10B61/22 ,  H10N50/01 ,  H10N50/85 ,  H01F10/3286

Abstract: A magnetic tunnel junction (MTJ) element is provided. The MTJ element includes a buffer layer, a seed layer disposed over the buffer layer, a first ferromagnetic layer disposed over the seed layer, a tunnel barrier layer disposed over the first ferromagnetic layer and a second ferromagnetic layer disposed over the tunnel barrier layer. The seed layer includes a Cobalt (Co)-based film. The buffer layer includes cobalt (Co) and hafnium (Hf). The buffer layer is alloyed with chromium and has chromium content up to 20 at. %. The MTJ element in accordance with the present disclosure exhibits a low resistance desired for a low-power write operation, and a high TMR coefficient desired for a low bit-error-rate (BER) read operation.

公开(公告)号：US12075711B2

公开(公告)日：2024-08-27

申请号：US17587888

申请日：2022-01-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shy-Jay Lin ,  Mingyuan Song

IPC: H10N52/80 ,  H10B61/00 ,  H10N50/85 ,  H10N52/00 ,  H10N52/01

CPC classification number: H10N52/80 ,  H10B61/22 ,  H10N50/85 ,  H10N52/00 ,  H10N52/01

Abstract: A spin-orbit-torque (SOT) magnetic device includes a bottom metal layer, a first magnetic layer, as a magnetic free layer, disposed over the bottom metal layer, a spacer layer disposed over the first magnetic layer, and a second magnetic layer disposed over the spacer layer. The first magnetic layer includes a lower magnetic layer, a middle layer made of nonmagnetic layer and an upper magnetic layer.

公开(公告)号：US20240284804A1

公开(公告)日：2024-08-22

申请号：US18642280

申请日：2024-04-22

Applicant: Godo Kaisha IP Bridge 1

Inventor： Shinji YUASA

IPC: H10N50/85 ,  B82Y10/00 ,  B82Y25/00 ,  G11C11/15 ,  G11C11/16 ,  H01F10/13 ,  H01F10/32 ,  H10B53/30 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N59/00

CPC classification number: H10N50/85 ,  B82Y25/00 ,  G11C11/15 ,  G11C11/16 ,  G11C11/161 ,  H01F10/132 ,  H01F10/3254 ,  H01L28/55 ,  H10B53/30 ,  H10B61/00 ,  H10B61/22 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  B82Y10/00 ,  H10N59/00

Abstract: The output voltage of an MRAM is increased by means of an Fe(001)/MgO(001)/Fe(001) MTJ device, which is formed by microfabrication of a sample prepared as follows: A single-crystalline MgO (001) substrate is prepared. An epitaxial Fe(001) lower electrode (a first electrode) is grown on a MgO(001) seed layer at room temperature, followed by annealing under ultrahigh vacuum. A MgO(001) barrier layer is epitaxially formed on the Fe(001) lower electrode (the first electrode) at room temperature, using a MgO electron-beam evaporation. A Fe(001) upper electrode (a second electrode) is then formed on the MgO(001) barrier layer at room temperature. This is successively followed by the deposition of a Co layer on the Fe(001) upper electrode (the second electrode). The Co layer is provided so as to increase the coercive force of the upper electrode in order to realize an antiparallel magnetization alignment.

公开(公告)号：US12069964B2

公开(公告)日：2024-08-20

申请号：US17811581

申请日：2022-07-09

Applicant: Integrated Silicon Solution, (Cayman) Inc.

Inventor： Kuk-Hwan Kim ,  Dafna Beery ,  Amitay Levi ,  Andrew J. Walker

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  G11C11/161 ,  H10B61/22 ,  H10N50/01 ,  H10N50/85

Abstract: A method for manufacturing a magnetic random access memory array incudes forming a source region within a surface of a substrate, forming an array of three-dimensional (3D) structures over the substrate, each 3D structure being separated from an adjacent 3D structure by a cavity region, depositing a channel material on a surface of at least one sidewall of each 3D structure, depositing a gate dielectric material over the channel material on the surface of the at least one sidewall of each 3D structure, forming a first isolation region in each cavity region between adjacent 3D structures over the substrate, and forming a first gate region over the first isolation region in each cavity region.

公开(公告)号：US12063792B2

公开(公告)日：2024-08-13

申请号：US18207654

申请日：2023-06-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Hung-Yueh Chen ,  Wei Chen

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10B61/22 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.