公开(公告)号：US11915755B2

公开(公告)日：2024-02-27

申请号：US17580591

申请日：2022-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Hsien Huang ,  Hsin-Chih Yu ,  Meng-Ping Chuang ,  Li-Ping Huang ,  Yu-Fang Chen

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

公开(公告)号：US20230282261A1

公开(公告)日：2023-09-07

申请号：US17707934

申请日：2022-03-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Jen-Yu Wang ,  Li-Ping Huang ,  Yi-Ting Wu ,  Jia-Rong Wu ,  Chun-Hsien Huang

IPC: G11C11/16 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22

CPC classification number: G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

Abstract: The present invention provides a spin-orbit torque magnetic random access memory (SOT-MRAM) circuit, including a read transistor pair with two read transistors in parallel, a write transistor pair with two write transistors in parallel, a SOT memory cell with a magnetic tunnel junction (MTJ) and a SOT layer, wherein one end of the MTJ is connected to the source of the read transistor pair and the other end of the MTJ is connected to the SOT layer, and one end of the SOT layer is connected to a source line and the other of the SOT layer is connected to the source of the write transistor pair, a read bit line is connected to the drain of the read transistor pair and a write bit line is connected to the drain of the read transistor.

公开(公告)号：US20230207648A1

公开(公告)日：2023-06-29

申请号：US17583225

申请日：2022-01-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chien-Hung Chen ,  Li-Ping Huang ,  Chun-Yen Tseng

IPC: H01L29/423 ,  H01L27/11 ,  G11C11/412 ,  G11C5/06 ,  H01L29/78

CPC classification number: H01L29/42376 ,  G11C5/063 ,  G11C11/412 ,  H01L27/1104 ,  H01L29/7851

Abstract: The present invention provides a layout pattern of static random access memory, comprising a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

公开(公告)号：US11489010B2

公开(公告)日：2022-11-01

申请号：US17006928

申请日：2020-08-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Shu-Ru Wang ,  Yu-Tse Kuo ,  Chang-Hung Chen ,  Yi-Ting Wu ,  Shu-Wei Yeh ,  Ya-Lan Chiou ,  Chun-Hsien Huang

IPC: H01L27/22 ,  H01L43/02

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.

公开(公告)号：US10861549B1

公开(公告)日：2020-12-08

申请号：US16503617

申请日：2019-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chun-Hsien Huang ,  Chih-Wei Tsai ,  Hsin-Chih Yu ,  Shu-Ru Wang

IPC: G11C15/00 ,  G11C15/04 ,  H01L27/11

Abstract: A ternary content addressable memory unit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The first inverter includes an input terminal, and an output terminal coupled to a first node. The second inverter includes an input terminal coupled to the first node and an output terminal coupled to the input terminal of the first inverter. The third inverter includes an input terminal coupled to a second node and an output terminal. The fourth inverter includes an input terminal coupled to the output terminal of the third inverter and an output terminal coupled to the second node.

公开(公告)号：US10468420B2

公开(公告)日：2019-11-05

申请号：US16028442

申请日：2018-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang

IPC: H01L21/336 ,  H01L27/11 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/84

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent PU (pull-up) FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

公开(公告)号：US10381056B2

公开(公告)日：2019-08-13

申请号：US15992130

申请日：2018-05-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Yu Lu ,  Chun-Hsien Huang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Shou-Sian Chen ,  Koji Nii ,  Yuichiro Ishii

IPC: G11C8/16 ,  G11C8/08 ,  H01L27/11 ,  G11C11/412 ,  G11C7/12

Abstract: A dual port static random access memory (DPSRAM) cell includes a first power line, a first bit line and a second bit line. The first power line is disposed between a first word line and a second word line. The first bit line is disposed between the first word line and the first power line. The second bit line is disposed between the second word line and the first power line.

公开(公告)号：US10366756B1

公开(公告)日：2019-07-30

申请号：US16104946

申请日：2018-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chun-Hsien Huang ,  Hsin-Chih Yu ,  Shu-Ru Wang

IPC: G11C15/00 ,  G11C15/04

Abstract: A control circuit for a ternary content-addressable memory includes a first logic unit and a second logic unit. The first logic unit is coupled to a first storage unit, a second storage unit, a first search line, a second search line, a reference voltage terminal, and a match line. The second logic unit is coupled to the first storage unit, the second storage unit, the first search line, the second search line, a first power supply line and a second power supply line. When voltages at the first search line and the second search line match voltages at the first storage unit and the second storage unit, the second logic unit provides a path for electrically connecting the first power supply line to the second power supply line.

公开(公告)号：US10050046B2

公开(公告)日：2018-08-14

申请号：US15691764

申请日：2017-08-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/66

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent PU (pull-up) FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

公开(公告)号：US09379119B1

公开(公告)日：2016-06-28

申请号：US14749623

申请日：2015-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Jyh-Shyang Jenq

IPC: H01L23/48 ,  H01L27/11 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/1104 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0924

Abstract: A static random access memory (SRAM) is disclosed. The SRAM includes a plurality of SRAM cells on a substrate, in which each of the SRAM cells further includes: a gate structure on the substrate, a plurality of fin structures disposed on the substrate, where each fin structure is arranged perpendicular to the arrangement direction of the gate structure, a first interlayer dielectric (ILD) layer around the gate structure, a first contact plug in the first ILD layer, where the first contact plug is strip-shaped and contacts two different fin structures; and a second ILD layer on the first ILD layer.

Abstract translation: 公开了一种静态随机存取存储器（SRAM）。 SRAM包括在衬底上的多个SRAM单元，其中每个SRAM单元还包括：衬底上的栅极结构，设置在衬底上的多个鳍结构，其中每个鳍结构垂直于排列方向排列 栅极结构周围的第一层间电介质（ILD）层，第一ILD层中的第一接触插塞，其中第一接触插塞为带状并接触两个不同的翅片结构; 和第一ILD层上的第二ILD层。