公开(公告)号：US11915755B2

公开(公告)日：2024-02-27

申请号：US17580591

申请日：2022-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Hsien Huang ,  Hsin-Chih Yu ,  Meng-Ping Chuang ,  Li-Ping Huang ,  Yu-Fang Chen

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

公开(公告)号：US20240161818A1

公开(公告)日：2024-05-16

申请号：US18071658

申请日：2022-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Li-Ping Huang ,  Yu-Fang Chen ,  Chun-Yen Tseng ,  Tzu-Feng Chang ,  Chun-Chieh Chang

IPC: G11C11/412 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC classification number: G11C11/412 ,  H01L27/1104 ,  H01L29/6681 ,  H01L29/7851

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

公开(公告)号：US20230197153A1

公开(公告)日：2023-06-22

申请号：US17580591

申请日：2022-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Hsien Huang ,  Hsin-Chih Yu ,  Meng-Ping Chuang ,  Li-Ping Huang ,  Yu-Fang Chen

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

公开(公告)号：US12224001B2

公开(公告)日：2025-02-11

申请号：US18071658

申请日：2022-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Li-Ping Huang ,  Yu-Fang Chen ,  Chun-Yen Tseng ,  Tzu-Feng Chang ,  Chun-Chieh Chang

IPC: G11C11/412 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.