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    LAYOUT PATTERN FOR STATIC RANDOM ACCESS MEMORY
    1.
    发明申请
    LAYOUT PATTERN FOR STATIC RANDOM ACCESS MEMORY 审中-公开

    公开(公告)号：US20200027869A1

    公开(公告)日：2020-01-23

    申请号：US16101528

    申请日：2018-08-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shu-Wei Yeh ,  Chang-Hung Chen

    IPC: H01L27/02 ,  G11C11/412 ,  G11C8/16 ,  G11C11/417 ,  H01L27/11

    Abstract: The present invention provides a layout pattern of a static random access memory (SRAM), comprising at least one substrate, two SRAM units on the substrate, respectively located in a first region and a second region which is adjacent to the first region. Each of the SRAM units includes a first inverter coupled to a second inverter and configured to form a latching circuit, the first inverter includes a first pull-up transistor (PU1) and a first pull-down transistor (PD1), the second inverter includes a second pull-up transistor (PU2) and a second pull-down transistor (PD2). A dummy layer crossing the first a region and the second region, and between the PD1 in the first region and the PD1 in the second region, and a contact structure on the dummy layer, electrically connected to a voltage source Vss.

    Layout pattern of static random access memory and the manufacturing method thereof
    4.
    发明授权
    Layout pattern of static random access memory and the manufacturing method thereof 有权

    公开(公告)号：US11502088B2

    公开(公告)日：2022-11-15

    申请号：US17163571

    申请日：2021-02-01

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Chi Lee ,  Shu-Wei Yeh ,  Chang-Hung Chen

    IPC: H01L27/11 ,  H01L21/8238 ,  H01L27/092

    Abstract: A layout pattern of static random access memory at least includes a substrate, a plurality of fin structures on the substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate, the plurality of transistors include, a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first pass gate transistor PG1, a second pass gate transistor PG2, a first read transistor RPD and a second read transistor RPG, and an additional fin structure, the additional fin structure is located between the fin structure of the first pass gate transistor PG1 and the fin structure of the second read transistor RPG.

    Layout pattern of static random access memory and the manufacturing method thereof
    8.
    发明申请
    Layout pattern of static random access memory and the manufacturing method thereof 有权

    公开(公告)号：US20220216220A1

    公开(公告)日：2022-07-07

    申请号：US17163571

    申请日：2021-02-01

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Chi Lee ,  Shu-Wei Yeh ,  Chang-Hung Chen

    IPC: H01L27/11 ,  H01L27/092 ,  H01L21/8238

    Abstract: A layout pattern of static random access memory at least includes a substrate, a plurality of fin structures on the substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate, the plurality of transistors include, a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first pass gate transistor PG1, a second pass gate transistor PG2, a first read transistor RPD and a second read transistor RPG, and an additional fin structure, the additional fin structure is located between the fin structure of the first pass gate transistor PG1 and the fin structure of the second read transistor RPG.

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