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1.发明授权公开(公告)号：US12068030B2
公开(公告)日：2024-08-20
申请号：US17524771
申请日：2021-11-12
发明人： Po-Hao Tseng , Feng-Min Lee , Ming-Hsiu Lee
CPC分类号： G11C15/046 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26
摘要： The application provides a content addressable memory (CAM) cell, a CAM memory device and an operation method thereof, and a method for searching and comparing data. The CAM cell includes a first flash memory cell having a first terminal for receiving a first search voltage; and a second flash memory cell having a first terminal for receiving a second search voltage, a second terminal of the first flash memory cell electrically connected to a second terminal of the second flash memory cell, wherein the first flash memory cell and the second flash memory cell are serially connected; and a storage data of the CAM cell is based on a combination of a plurality of threshold voltages of the first flash memory cell and the second flash memory cell.
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2.发明公开公开(公告)号：US20240233818A1
公开(公告)日：2024-07-11
申请号：US18442857
申请日：2024-02-15
申请人： MacroGenics, Inc.
发明人： Liqin LIU , Chia-Ying Kao LAM , Gundo DIEDRICH , Leslie S. JOHNSON , Paul A. MOORE , Ezio BONVINI
CPC分类号： G11C13/0026 , G11C13/004 , G11C15/00 , G11C2013/0045
摘要： The present invention is directed to binding molecules that possess one or more epitope-binding sites specific for an epitope of CD137 and one or more epitope-binding sites specific for an epitope of a tumor antigen (“TA”) (e.g., a “CD137×TA Binding Molecule”). In one embodiment, such CD137×TA Binding Molecules will be bispecific molecules, especially bispecific tetravalent diabodies, that are composed of two, three, four or more than four polypeptide chains and possessing two epitope-binding sites each specific for an epitope of CD137 and two epitope-binding sites each specific for an epitope of a TA. Alternatively, such CD137×TA Binding Molecules will be bispecific molecules, especially bispecific trivalent binding molecules composed of three or more polypeptide chains and possessing one or two epitope-binding sites each specific for an epitope of CD137 and one or two epitope-binding sites each specific for an epitope of a TA. The CD137×TA Binding Molecules of the invention are capable of simultaneous binding to CD137, and a TA. The invention is directed to pharmaceutical compositions that contain any such CD137×TA Binding Molecules. The invention is additionally directed to methods for the use of such molecules in the treatment of cancer and other diseases and conditions. The invention also provides novel CD137-binding molecules, and HER2/neu-binding molecules, as well as derivatives thereof and uses thereof.
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公开(公告)号：US12008068B2
公开(公告)日：2024-06-11
申请号：US18354679
申请日：2023-07-19
申请人： GSI Technology Inc.
发明人： Avidan Akerib , Pat Lasserre
IPC分类号： G06F17/16 , G06F3/06 , G06N3/04 , G06N3/063 , G06N3/08 , G11C7/10 , G11C7/22 , G11C8/10 , G11C15/00
CPC分类号： G06F17/16 , G06F3/0604 , G06F3/0644 , G06F3/0659 , G06F3/067 , G06N3/04 , G06N3/08 , G11C7/22 , G11C15/00 , G06N3/063 , G11C7/1006 , G11C8/10
摘要： A device for in memory vector-matrix multiplication includes a memory array and in-memory logic. The memory array has at least two sections and stores a multiplier matrix. The memory array also receives and stores an input multiplicand arranged in a vector such that the operands of the vector-matrix multiplication are located on a same column of the memory array. Each of the sections is one of: a volatile memory array, a non-volatile memory array, a destructive memory array and a non-destructive memory array. The in-memory logic computes an output of the vector-matrix multiplication using the stored input vector and the stored multiplier matrix. The memory array is one of the following type of memory array: RAM, DRAM, SRAM, Re-RAM, ZRAM, MRAM and Memristor.
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公开(公告)号：US11892902B2
公开(公告)日：2024-02-06
申请号：US17470342
申请日：2021-09-09
发明人： YanLan Liu
CPC分类号： G06F11/0793 , G06F11/073 , G11C15/00 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/26
摘要： The present disclosure provides a content addressable memory (CAM) for repairing firmware of multi-plane read operations in a flash memory device. The CAM comprises a set of CAM registers configured to store a mapping table. The mapping table comprises a plurality of old addresses, each old address corresponding to a new address. The CAM also comprises N comparators coupling to the set of CAM registers, and configured to compare the old addresses with N input signals for performing the multi-plane read operations on N memory planes, wherein N is an integer greater than 1. The CAM further comprises N multiplexers coupling to the N comparators respectively and to the set of CAM registers, and configured to generate N output signals for the multi-plane read operations. At least one of the N output signals comprises the new address according to the mapping table and a comparison output by the comparators.
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5.发明授权公开(公告)号：US11532337B1
公开(公告)日：2022-12-20
申请号：US17383562
申请日：2021-07-23
发明人： Ming-Hsiu Lee , Po-Hao Tseng
摘要： A multilevel content addressable memory, a multilevel coding method and a multilevel searching method are provided. The multilevel coding method includes the following steps. A highest decimal value of a multilevel-bit binary data is obtained. A length of a digital string data is set as being the highest decimal value of the multilevel-bit binary data. The multilevel-bit binary data is converted into the digital string data. If a content of the multilevel-bit binary data is an exact value, a number of an indicating bit in the digital string data is the exact value.
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公开(公告)号：US20220391280A1
公开(公告)日：2022-12-08
申请号：US17470342
申请日：2021-09-09
发明人： YanLan Liu
摘要： The present disclosure provides a content addressable memory (CAM) for repairing firmware of multi-plane read operations in a flash memory device. The CAM comprises a set of CAM registers configured to store a mapping table. The mapping table comprises a plurality of old addresses, each old address corresponding to a new address. The CAM also comprises N comparators coupling to the set of CAM registers, and configured to compare the old addresses with N input signals for performing the multi-plane read operations on N memory planes, wherein N is an integer greater than 1. The CAM further comprises N multiplexers coupling to the N comparators respectively and to the set of CAM registers, and configured to generate N output signals for the multi-plane read operations. At least one of the N output signals comprises the new address according to the mapping table and a comparison output by the comparators.
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公开(公告)号：US11475953B1
公开(公告)日：2022-10-18
申请号：US17377396
申请日：2021-07-16
发明人： Chun-Yen Tseng , Yu-Tse Kuo , Shu-Ru Wang , Chun-Hsien Huang , Hsin-Chih Yu , Meng-Ping Chuang , Li-Ping Huang
摘要： The invention provides a semiconductor layout pattern, the semiconductor layout pattern includes a substrate, a plurality of ternary content addressable memories (TCAM) are arranged on the substrate, the layout of at least two TCAM is mirror symmetric with each other along an axis of symmetry, and the two TCAM are connected to the same search line (SL) together.
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8.发明申请公开(公告)号：US20220200623A1
公开(公告)日：2022-06-23
申请号：US17133609
申请日：2020-12-23
申请人： Intel Corporation
发明人： JAMES GUILFORD , VINODH GOPAL , DANIEL CUTTER , KIRK YAP
摘要： Apparatus and method for efficient compression block decoding using content-addressable structure for header processing. For example, one embodiment of an apparatus comprises: a header parser to extract a sequence of tokens and corresponding length values from a header of a compression block, the tokens and corresponding length values associated with a type of compression used to compress a payload of the compression block; and a content-addressable data structure builder to construct a content-addressable data structure based on the tokens and length values, the content-addressable data structure builder to write an entry in the content-addressable data structure comprising a length value and a count value, the count value indicating a number of times the length value was previously written to an entry in the content-addressable data structure.
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公开(公告)号：US11328775B2
公开(公告)日：2022-05-10
申请号：US17065516
申请日：2020-10-07
发明人： Po-Hao Tseng , Ming-Hsiu Lee , Feng-Min Lee
摘要： A ternary content addressable memory and a memory cell thereof are provided. The ternary content addressable memory cell includes a first transistor and a second transistor. The first transistor has a gate to receive a selection signal. A first end of the first transistor is coupled to a match line. A second end of the first transistor is coupled to a source line. The second transistor has a gate to receive an inverted selection signal. A first end of the second transistor is coupled to the match line. A second end of the second transistor is coupled to the source line. The first and second transistors have charge storage structures.
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公开(公告)号：US11190429B2
公开(公告)日：2021-11-30
申请号：US16778674
申请日：2020-01-31
IPC分类号： H04L12/26 , G06F9/451 , G06F11/30 , G11C15/00 , H04L12/813 , H04L29/08 , H04L12/743 , H04L12/947 , H04L12/931 , H04L29/06 , H04L12/911
摘要： System and method for using multiple global identification subnet prefix values in a network switch environment in a high performance computing environment. A packet is received from a network fabric by a first Host Channel Adapter (HCA). The packet has a header portion including a destination subnet prefix identifying a destination subnet of the network fabric. The network HCA is allowed to receive the first packet from a port of the network HCA by selectively determining a logical state of a flag and, selectively in accordance with a predetermined logical state of the flag, ignoring the destination subnet prefix identifying the destination subnet of the network fabric.
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