知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

1281 records (took 0.024 seconds)

    Multiple transistor architecture for three-dimensional memory arrays
    1.
    发明授权
    Multiple transistor architecture for three-dimensional memory arrays 有权

    公开(公告)号：US12119056B2

    公开(公告)日：2024-10-15

    申请号：US17701463

    申请日：2022-03-22

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi

    IPC: G11C13/00 ,  G11C16/04 ,  H10B43/20

    CPC classification number: G11C13/0026 ,  G11C13/0004 ,  G11C16/0483 ,  H10B43/20 ,  G11C2213/71

    Abstract: Methods, systems, and devices for multiple transistor architecture for three-dimensional memory arrays are described. A memory device may include conductive pillars coupled with an access line using two transistors positioned between the conductive pillar and the access line. As part of an access operation for a memory cell coupled with the conductive pillar, the memory device may be configured to bias the access line to a first voltage and activate the two transistors using a second voltage to couple the conductive pillar with the access line. Additionally, the memory device may be configured to bias a gate of a first transistor and a gate of a second transistor coupling an unselected conductive pillar with the access line to a third and fourth voltage, respectively, which may deactivate at least one of the first or second transistor during the access operation and isolate the unselected conductive pillar from the access line.

    METHOD FOR PROGRAMMING MEMORY
    2.
    发明公开
    METHOD FOR PROGRAMMING MEMORY 审中-公开

    公开(公告)号：US20240339156A1

    公开(公告)日：2024-10-10

    申请号：US18748196

    申请日：2024-06-20

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： I-Che Lee ,  Huai-Ying Huang

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004

    Abstract: A method includes setting a current level of a write signal to a first non-zero value for a first period of time. The write signal is provided to a memory element during the first period of time. The current level of the write signal is adjusted from the first non-zero value to a second non-zero value, different from the first non-zero value, for a second period of time. The write signal is provided to the memory element during the second period of time. The current level of the write signal is adjusted from the second non-zero value to a third value, different from the first non-zero value and different from the second non-zero value, for a third period of time. The write signal is provided to the memory element during the third period of time.

    Decoder architecture for memory device
    4.
    发明授权
    Decoder architecture for memory device 有权

    公开(公告)号：US12051463B2

    公开(公告)日：2024-07-30

    申请号：US17864004

    申请日：2022-07-13

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi ,  Jeffrey E. Koelling ,  Hari Giduturi ,  Riccardo Muzzetto ,  Corrado Villa

    IPC: G11C13/00

    CPC classification number: G11C13/0026 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0033

    Abstract: Methods, systems, and devices for decoder architecture for memory device are described. An apparatus includes a memory array having a memory cell and an access line coupled with the cell and a decoder having a first stage and a second stage. The decoder supplying a first voltage during a first access operation and a second voltage during a second access operation to the access line. The second stage of the decoder includes a first transistor that supplies the first voltage based on a third voltage at the source of the first transistor exceeding a fourth voltage at a gate of the first transistor and a first threshold voltage. The second stage includes a second transistor that supplies the second voltage based on a fifth voltage at a gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage.

    IN-MEMORY COMPUTATION SYSTEM WITH COMPACT STORAGE OF SIGNED COMPUTATIONAL WEIGHT DATA
    7.
    发明公开
    IN-MEMORY COMPUTATION SYSTEM WITH COMPACT STORAGE OF SIGNED COMPUTATIONAL WEIGHT DATA 审中-公开

    公开(公告)号：US20240176586A1

    公开(公告)日：2024-05-30

    申请号：US17994817

    申请日：2022-11-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Marcella CARISSIMI ,  Paolo Sergio ZAMBOTTI ,  Riccardo ZURLA

    IPC: G06F7/544 ,  G11C13/00

    CPC classification number: G06F7/5443 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028

    Abstract: An IMC circuit includes a memory cells arranged in matrix. Computational weights for an IMC operation are stored in groups of cells. Each row of groups of cells includes a positive and negative word linen. Each column of groups of cells includes a bit line. The IMC operation includes a first elaboration where a word line signal is applied to the positive/negative word line of the group of cells depending on the positive/negative sign, respectively, of the coefficient data, with a positive MAC output on the bit line. In a second elaboration, a word line signal is applied to the negative/positive word line of the group of cells depending on the positive/negative sign, respectively, of the coefficient data, with a negative MAC output on the bit line. The IMC operation result is obtained from a difference between the positive and negative MAC operations.

    MATCHING PATTERNS IN MEMORY ARRAYS
    10.
    发明公开
    MATCHING PATTERNS IN MEMORY ARRAYS 审中-公开

    公开(公告)号：US20240153556A1

    公开(公告)日：2024-05-09

    申请号：US18515692

    申请日：2023-11-21

    Applicant: Lodestar Licensing Group LLC

    Inventor： Dmitri Yudanov

    IPC: G11C13/00 ,  G06F16/2458

    CPC classification number: G11C13/004 ,  G06F16/2468 ,  G11C13/0026 ,  G06N3/04

    Abstract: Systems and methods for performing a pattern matching operation in a memory device are disclosed. The memory device may include a controller and memory arrays where the memory arrays store different patterns along bit lines. An input pattern is applied to the memory array(s) to determine whether the pattern is stored in the memory device. Word lines may be activated in series or in parallel to search for patterns within the memory array. The memory array may include memory cells that store binary digits, discrete values or analog values.

Patent Agency Ranking