-
公开(公告)号：US12108692B2
公开(公告)日：2024-10-01
申请号：US17473359
申请日：2021-09-13
Applicant: International Business Machines Corporation
Inventor： Heng Wu , Tian Shen , Kevin W. Brew , Jingyun Zhang
CPC classification number: H10N70/253 , H10N70/063 , H10N70/231 , H10N70/823 , H10N70/8413 , H10N70/8828
Abstract: A phase change memory, a system, and a method to prevent high resistance drift within a phase change memory through a phase change memory cell with three terminals and self-aligned metal contacts. The phase change memory may include a bottom electrode. The phase change memory may also include a heater proximately connected to the bottom electrode. The phase change memory may also include a phase change material proximately connected to the heater. The phase change memory may also include metal proximately connected to at least two sides of the phase change material. The phase change memory may also include three terminals, where a bottom terminal is located at an area proximately connected to the heater and two top terminals are located at areas proximately connected to the metal.
-
公开(公告)号：US12108611B2
公开(公告)日：2024-10-01
申请号：US16941170
申请日：2020-07-28
Applicant: SK hynix Inc.
Inventor： Jae Hyun Han , Se Ho Lee , Hyangkeun Yoo
CPC classification number: H10B63/30 , H10B63/82 , H10B63/84 , H10N70/24 , H10N70/245 , H10N70/253 , H10N70/823 , H10N70/841 , H10N70/8822 , H10N70/8828 , H10N70/883 , H10N70/8833 , H10N70/8836
Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a resistance change layer disposed on the substrate, a gate electrode layers disposed on the resistance change layer, and a first electrode pattern layer and a second electrode pattern layer that are disposed in the substrate and contact different portions of the resistance change layer. The resistance change layer includes movable oxygen vacancies or movable metal ions.
-
公开(公告)号：US12069870B2
公开(公告)日：2024-08-20
申请号：US16431885
申请日：2019-06-05
Applicant: CYBERSWARM, INC.
Inventor： Viorel-Georgel Dumitru , Cristina Besleaga Stan , Alin Velea , Aurelian-Catalin Galca
CPC classification number: H10B63/82 , G06N3/063 , H10B63/30 , H10N70/253 , H10N70/821 , H10N70/8613
Abstract: A synapse crossbar array device is provided. The synapse crossbar array device includes a plurality of Indium-Gallium-Zinc-Oxide (IGZO) thin film transistors (TFTs) and a plurality of IGZO resistive synapses. Each IGZO resistive synapse includes a IGZO resistive layer, a first electrical contact electrically coupled to one of the plurality of IGZO TFTs and a second electrical contact electrically connected to one of a plurality of column connection lines. The first electrical contact and the second electrical contact of each IGZO resistive synapse are disposed on the IGZO resistive layer of the resistive synapse. The synapse crossbar array device includes IGZO resistive synapses that have, each of them, an established resistance value. The synapse crossbar array may be fully transparent and may be integrated into the displays with which portable devices are provided.
-
公开(公告)号：US20240023468A1
公开(公告)日：2024-01-18
申请号：US18190901
申请日：2023-03-27
Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES , STMicroelectronics (Crolles 2) SAS , STMICROELECTRONICS SA
Inventor： Alain FLEURY , Stephane MONFRAY , Philippe CATHELIN , Bruno REIG , Vincent PUYAL
CPC classification number: H10N70/8613 , H10N70/231 , H10N70/253 , H10N70/841 , H10N70/8828
Abstract: The present description concerns a switch based on a phase-change material comprising: a region of the phase-change material; a heating element electrically insulated from the region of the phase-change material; and one or a plurality of pillars extending in the region of the phase-change material, the pillar(s) being made of a material having a thermal conductivity greater than that of the phase-change material.
-
5.发明授权
公开(公告)号：US11871684B2
公开(公告)日：2024-01-09
申请号：US17391444
申请日：2021-08-02
Applicant: SK hynix Inc.
Inventor： Jae Hyun Han
CPC classification number: H10N70/253 , H10N70/24 , H10N70/826 , H10N70/8413
Abstract: A semiconductor device includes a substrate and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer and at least one interlayer insulating layer that are alternately stacked over the substrate. The semiconductor device includes a hole pattern penetrating the gate structure over the substrate, and a gate insulating layer, a channel layer, a resistor layer, and a resistance changing layer sequentially disposed on a sidewall surface of the gate structure within the hole pattern. Each of the resistor layer and the resistance changing layer is disposed opposite to the gate insulating layer, based on the channel layer.
-
公开(公告)号：US20230380190A1
公开(公告)日：2023-11-23
申请号：US18361483
申请日：2023-07-28
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Chieh-Fei CHIU , Wen-Ting CHU , Yong-Shiuan TSAIR , Yu-Wen LIAO , Chih-Yang CHANG , Chin-Chieh YANG
CPC classification number: H10B63/30 , H10B51/30 , H10B51/40 , H10B61/22 , H10N50/01 , H10N50/80 , H10N70/021 , H10N70/063 , H10N70/068 , H10N70/231 , H10N70/253 , H10N70/841
Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.
-
7.发明授权
公开(公告)号：US11825758B2
公开(公告)日：2023-11-21
申请号：US16797391
申请日：2020-02-21
Applicant: Massachusetts Institute of Technology
Inventor： Jennifer Rupp , Juan Carlos Gonzalez Rosillo
CPC classification number: H10N70/8836 , C01G23/005 , H10N70/235 , H10N70/253 , C01P2002/72 , C01P2002/82 , C01P2004/03 , C01P2004/04 , C01P2006/40
Abstract: Resistive switching devices that contain lithium, including resistive switching devices containing a lithium titanate, and associated systems and methods are generally described. In some cases, the resistive switching device contains a lithium titanate-containing domain, a first electrode, and a second electrode. In some cases, the application of an electrical potential to the resistive switching device causes a change in resistance state of the lithium titanate-containing domain. The resistive switching devices described herein may be useful as memristors, and in applications that include Resistive-random access memory and neuromorphic computing.
-
8.发明公开
公开(公告)号：US20230301211A1
公开(公告)日：2023-09-21
申请号：US18122696
申请日：2023-03-16
Inventor： Jiyong Woo , Heebum Kang
CPC classification number: H10N70/253 , H10N70/245 , H10N70/8416 , G06N3/065 , H10N70/021
Abstract: Disclosed is a 3-terminal neuromorphic synaptic device including a substrate, a source electrode and a drain electrode provided on the substrate to be spaced apart from each other, a channel area provided on the substrate to be electrically connected to the source electrode and the drain electrode, between the source electrode and the drain electrode, an ion transport layer provided on the channel area, a gate electrode provided on the ion transport layer, and a voltage application part that applies a gate voltage to the gate electrode. The gate electrode is formed of at least one of an oxide-based material including mobile ions, a chalcogenide-based material including the mobile ions, and a nitride-based material including the mobile ions.
-
公开(公告)号：US11751405B2
公开(公告)日：2023-09-05
申请号：US17032155
申请日：2020-09-25
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Chieh-Fei Chiu , Wen-Ting Chu , Yong-Shiuan Tsair , Yu-Wen Liao , Chih-Yang Chang , Chin-Chieh Yang
IPC: H01L45/00 , H10B63/00 , H10B51/30 , H10B51/40 , H10B61/00 , H10N50/01 , H10N50/80 , H10N70/00 , H10N70/20
CPC classification number: H10B63/30 , H10B51/30 , H10B51/40 , H10B61/22 , H10N50/01 , H10N50/80 , H10N70/021 , H10N70/063 , H10N70/068 , H10N70/231 , H10N70/253 , H10N70/841
Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.
-
公开(公告)号：US12022667B2
公开(公告)日：2024-06-25
申请号：US17521347
申请日：2021-11-08
Applicant: National University of Singapore
Inventor： Xuewei Feng , Kah Wee Ang
CPC classification number: H10B63/84 , G11C13/0002 , H10N70/011 , H10N70/253
Abstract: This disclosure describes a self-selective multi-terminal memtransistor suitable for use in crossbar array circuits. In particular, the memtransistor comprises a sapphire substrate that has a single-layer of polycrystalline molybdenum disulphide (MoS2) thin film formed on the surface of the substrate, wherein the MoS2 thin film comprise MoS2 grains that are oriented along terraces provided on the surface of the substrate. The memtransistor has a drain electrode and a source electrode that is formed on the MoS2 thin film such that a channel is defined in the MoS2 thin film between the drain and source electrodes, and a gate electrode formed above the channel, whereby the gate electrode is isolated from the channel by a gate dielectric layer.
