公开(公告)号：US20240347107A1

公开(公告)日：2024-10-17

申请号：US18616989

申请日：2024-03-26

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Radhakrishna Kotti ,  Rajasekhar Venigalla

IPC: G11C13/00 ,  H01L23/522 ,  H01L23/528 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: G11C13/0028 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  H01L23/5226 ,  H01L23/528 ,  H10B63/84 ,  H10N70/231 ,  H10N70/826 ,  G11C2213/52 ,  G11C2213/71 ,  H10N70/841 ,  H10N70/8825

Abstract: Methods, systems, and devices supporting a socket design for a memory device are described. A die may include one or more memory arrays, which each may include any number of word lines and any number of bit lines. The word lines and the bit lines may be oriented in different directions, and memory cells may be located at the intersections of word lines and bit lines. Sockets may couple the word lines and bit lines to associated drivers, and the sockets may be located such that memory cells farther from a corresponding word line socket are nearer a corresponding bit line socket, and vice versa. For example, sockets may be disposed in rows or regions that are parallel to one another, and which may be non-orthogonal to the corresponding word lines and bit lines.

公开(公告)号：US12094965B2

公开(公告)日：2024-09-17

申请号：US18429202

申请日：2024-01-31

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach

IPC: H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/412 ,  G11C16/02 ,  G11C16/04 ,  H10B10/00 ,  H10B12/00 ,  H10B43/20 ,  H10B63/00 ,  H10B69/00

CPC classification number: H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/412 ,  G11C16/02 ,  G11C16/0483 ,  H01L29/7841 ,  H10B10/12 ,  H10B12/20 ,  H10B43/20 ,  H10B63/30 ,  H10B69/00 ,  G11C2213/71

Abstract: 3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer—which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; second metal layer overlaying first metal layer; a second level including second transistors, first memory cells and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells and include at least one sense amplifier; third metal layer disposed above third level; fourth metal layer includes global power distribution grid, has a thickness at least twice the second metal layer, disposed above third metal layer; fourth level includes single-crystal silicon, atop fourth metal layer.

公开(公告)号：US12087361B2

公开(公告)日：2024-09-10

申请号：US18177320

申请日：2023-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bilal Ahmad Janjua ,  Jongryul Kim ,  Venkataramana Gangasani ,  Jungyu Lee

IPC: G11C13/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C2013/0078 ,  G11C2213/71 ,  G11C2213/72 ,  H10B63/24 ,  H10B63/84 ,  H10N70/231 ,  H10N70/8413 ,  H10N70/8828

Abstract: A memory device includes a plurality of memory cells, each including a switching device and an information storage device connected to the switching device and having a phase change material, the plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a decoder circuit determining at least one of the plurality of memory cells to be a selected memory cell, and a program circuit configured to input a programming current to the selected memory cell to perform a programming operation and configured to detect a resistance of the selected memory cell to adjust a magnitude of the programming current.

公开(公告)号：US12080345B2

公开(公告)日：2024-09-03

申请号：US17402291

申请日：2021-08-13

Applicant: SK hynix Inc.

Inventor： Dong Keun Kim

IPC: G11C13/00 ,  G11C11/16 ,  H10B63/00 ,  H10N50/85 ,  H10N70/00 ,  H10N70/20

CPC classification number: G11C13/0004 ,  G11C11/161 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/79 ,  H10B63/24 ,  H10N50/85 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8413 ,  H10N70/8828

Abstract: A memory device may include a bank layer and a control circuit layer. The bank layer may be arranged on a semiconductor substrate. The bank layer may include a plurality of mats. Each of the mats may include a plurality of stacked decks. Each of the decks may include a plurality of memory cells. The control circuit layer may be arranged between the semiconductor substrate and the bank layer. The control circuit layer may include a plurality of control circuit regions corresponding to the mats, respectively. The stacked decks may include a plurality of stacked word lines and a plurality of stacked bit lines intersected with the stacked word lines. A word line decoder, for controlling the word lines, and a bit line decoder, for controlling the bit lines, may be alternately and repeatedly arranged in the control circuit layer.

公开(公告)号：US12040014B2

公开(公告)日：2024-07-16

申请号：US17970756

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Koushik Banerjee ,  Isaiah O. Gyan ,  Robert Cassel ,  Jian Jiao ,  William L. Cooper ,  Jason R. Johnson ,  Michael P. O'Toole

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/79

Abstract: Methods, systems, and devices supporting configurable resistivities for lines in a memory device, such as access lines in a memory array are described. For example, metal lines at different levels of a memory device may be oxidized to different extents in order for the lines at different levels of the memory device to have different resistivities. This may allow the resistivity of lines to be tuned on a level-by-level basis without altering the fabrication techniques and related parameters used to initially form the lines at the different levels, which may have benefits related to at least reduced cost and complexity. Lines may be oxidized to a controlled extent using either a dry or wet process.

公开(公告)号：US20240237358A1

公开(公告)日：2024-07-11

申请号：US18407074

申请日：2024-01-08

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Corrado Villa ,  Stefan Frederik Schippers ,  Efrem Bolandrina

IPC: H10B63/00 ,  G11C13/00

CPC classification number: H10B63/34 ,  G11C13/0004 ,  G11C13/003 ,  H10B63/845 ,  G11C2213/71 ,  G11C2213/79

Abstract: The present disclosure provides a memory device and accessing/de-selecting methods thereof. The memory device comprises a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein a memory cell is accessed through a word line and a digit line orthogonal to each other, and the digit line is in a form of conductive pillar extending vertically; a pillar selection layer formed under the memory layer and having thin film transistors (TFTs) formed therein for accessing memory cells; and a peripheral circuit layer formed under the pillar selection layer and having a sense amplifier and a decoding circuitry for word lines and bit lines, wherein a TFT is configured for each pillar.

公开(公告)号：US20240221829A1

公开(公告)日：2024-07-04

申请号：US18409992

申请日：2024-01-11

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer ,  Mattia Robustelli ,  Alessandro Sebastiani

IPC: G11C13/00

CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71

Abstract: Methods, systems, and devices for a cross-point pillar architecture for memory arrays are described. Multiple selector devices may be configured to access or activate a pillar within a memory array, where the selector devices may each be or include a chalcogenide material. A pillar access line may be coupled with multiple selector devices, where each selector device may correspond to a pillar associated with the pillar access line. Pillar access lines on top and bottom of the pillars of the memory array may be aligned in a square or rectangle formation, or in a hexagonal formation. Pillars and corresponding selector devices on top and bottom of the pillars may be located at overlapping portions of the pillar access lines, thereby forming a cross point architecture for pillar selection or activation. The selector devices may act in pairs to select or activate a pillar upon application of a respective selection voltage.

公开(公告)号：US20240065000A1

公开(公告)日：2024-02-22

申请号：US18169436

申请日：2023-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yumin Kim ,  Jooheon Kang ,  Sunho Kim ,  Seyun Kim ,  Garam Park ,  Hyunjae Song ,  Dongho Ahn ,  Seungyeul Yang ,  Myunghun Woo ,  Jinwoo Lee

IPC: H10B63/00 ,  G11C13/00 ,  G06N3/063

CPC classification number: H10B63/34 ,  G11C13/0007 ,  G11C13/003 ,  H10B63/845 ,  G06N3/063 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/79

Abstract: Provided are a nonvolatile memory device and an operating method thereof. The nonvolatile memory device may include a conductive pillar, a resistance change layer surrounding a side surface of the conductive pillar, a semiconductor layer surrounding a side surface of the resistance change layer, a gate insulating layer surrounding a side surface of the semiconductor layer, and a plurality of insulating patterns and a plurality of gate electrodes alternately arranged along a surface of the gate insulating layer. The plurality of insulating patterns and the plurality of gate electrodes may surround a side surface of the gate insulating layer.

公开(公告)号：US11877457B2

公开(公告)日：2024-01-16

申请号：US16976411

申请日：2020-05-25

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Corrado Villa ,  Stefan Frederik Schippers ,  Efrem Bolandrina

IPC: G11C11/00 ,  H10B63/00 ,  G11C13/00

CPC classification number: H10B63/34 ,  G11C13/003 ,  G11C13/0004 ,  H10B63/845 ,  G11C2213/71 ,  G11C2213/79

Abstract: The present disclosure provides a memory device and accessing/de-selecting methods thereof. The memory device comprises a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein a memory cell is accessed through a word line and a digit line orthogonal to each other, and the digit line is in a form of conductive pillar extending vertically; a pillar selection layer formed under the memory layer and having thin film transistors (TFTs) formed therein for accessing memory cells; and a peripheral circuit layer formed under the pillar selection layer and having a sense amplifier and a decoding circuitry for word lines and bit lines, wherein a TFT is configured for each pillar.

公开(公告)号：US20230307042A1

公开(公告)日：2023-09-28

申请号：US17701463

申请日：2022-03-22

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi

IPC: G11C13/00 ,  H01L27/11578 ,  G11C16/04

CPC classification number: G11C13/0026 ,  H01L27/11578 ,  G11C16/0483 ,  G11C13/0004 ,  G11C2213/71

Abstract: Methods, systems, and devices for multiple transistor architecture for three-dimensional memory arrays are described. A memory device may include conductive pillars coupled with an access line using two transistors positioned between the conductive pillar and the access line. As part of an access operation for a memory cell coupled with the conductive pillar, the memory device may be configured to bias the access line to a first voltage and activate the two transistors using a second voltage to couple the conductive pillar with the access line. Additionally, the memory device may be configured to bias a gate of a first transistor and a gate of a second transistor coupling an unselected conductive pillar with the access line to a third and fourth voltage, respectively, which may deactivate at least one of the first or second transistor during the access operation and isolate the unselected conductive pillar from the access line.