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公开(公告)号：US20220278273A1
公开(公告)日：2022-09-01
申请号：US17749289
申请日：2022-05-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： YUKIO HAYAKAWA , Jooheon Kang , Myunghun Woo , Gunwook Yoon , Doohee Hwang
Abstract: A vertical variable resistance memory device includes gate electrodes and a pillar structure. The gate electrodes are spaced apart from one another on a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate. The pillar structure extends in the vertical direction through the gate electrodes on the substrate. The pillar structure includes a vertical gate electrode extending in the vertical direction, a variable resistance pattern disposed on a sidewall of the vertical gate electrode, and a channel disposed on an outer sidewall of the variable resistance pattern. The channel and the vertical gate electrode contact each other.
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Patent Agency Ranking
2.发明授权公开(公告)号：US12082423B2
公开(公告)日：2024-09-03
申请号：US17679863
申请日：2022-02-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunmook Choi , Jooheon Kang , Sanghoon Kim , Jihong Kim
IPC: H10B63/00
CPC classification number: H10B63/34
Abstract: A semiconductor device includes a horizontal wiring layer on a substrate, a stack structure disposed on the horizontal wiring layer and including insulating layers and electrode layers alternately stacked on each other, and a pillar structure extending into the horizontal wiring layer and extending through the stack structure. The electrode layers include one or a plurality of selection lines adjacent to an uppermost end of the stack structure, and word lines surrounding the stack structure below the one or plurality of selection lines. The pillar structure includes a variable resistive layer, a channel layer between the variable resistive layer and the stack structure, a gate dielectric layer between the channel layer and the stack structure, and a blocking pattern disposed between the variable resistive layer and the channel layer and being adjacent to a first selection line among the one or plurality of selection lines.
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公开(公告)号：US20240215250A1
公开(公告)日：2024-06-27
申请号：US18340419
申请日：2023-06-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seyun KIM , Jooheon Kang , Yumin Kim , Garam Park , Hyunjae Song , Dongho Ahn , Seungyeul Yang , Myunghun Woo , Jinwoo Lee , Seungdam Hyun
CPC classification number: H10B43/35 , G11C16/0483 , H10B43/10 , H10B43/27
Abstract: A memory device including the vertical stack structure includes a gate electrode, a resistance change layer, a channel between the gate electrode and the resistance change layer, and an island structure between the resistance change layer and the channel and in contact with the resistance change layer and the channel, and a gate insulating layer between the gate electrode and the channel.
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公开(公告)号：US20240172457A1
公开(公告)日：2024-05-23
申请号：US18497027
申请日：2023-10-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngji Noh , Jongho Woo , Jooheon Kang , Kyunghoon Kim , Myunghun Woo
IPC: H10B63/00
CPC classification number: H10B63/845 , H10B63/34
Abstract: A vertical memory device may include a cell stacked structure on a substrate, wherein the cell stacked structure includes an insulation layer pattern and a gate pattern are alternately and repeatedly stacked, and wherein the cell stacked structure extends in a first direction parallel to an upper surface of the substrate, and wherein an edge portion in the first direction of the cell stacked region is disposed in the second region and has a step portion having a step shape; an etch stop structure on an upper surface of each of gate patterns of the step portion of the cell stacked structure, wherein the etch stop structure includes a transition metal oxide; an insulating interlayer covering the cell stacked structure; and a contact plug passing through the insulating interlayer and the etch stop structure, wherein the contact plug contacts the upper surface of each of the gate patterns.
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公开(公告)号：US11957071B2
公开(公告)日：2024-04-09
申请号：US17749289
申请日：2022-05-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yukio Hayakawa , Jooheon Kang , Myunghun Woo , Gunwook Yoon , Doohee Hwang
CPC classification number: H10N70/826 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/0069 , H10B63/34 , H10N70/841 , H10N70/8833
Abstract: A vertical variable resistance memory device includes gate electrodes and a pillar structure. The gate electrodes are spaced apart from one another on a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate. The pillar structure extends in the vertical direction through the gate electrodes on the substrate. The pillar structure includes a vertical gate electrode extending in the vertical direction, a variable resistance pattern disposed on a sidewall of the vertical gate electrode, and a channel disposed on an outer sidewall of the variable resistance pattern. The channel and the vertical gate electrode contact each other.
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公开(公告)号：US20240065000A1
公开(公告)日：2024-02-22
申请号：US18169436
申请日：2023-02-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yumin Kim , Jooheon Kang , Sunho Kim , Seyun Kim , Garam Park , Hyunjae Song , Dongho Ahn , Seungyeul Yang , Myunghun Woo , Jinwoo Lee
CPC classification number: H10B63/34 , G11C13/0007 , G11C13/003 , H10B63/845 , G06N3/063 , G11C2213/71 , G11C2213/75 , G11C2213/79
Abstract: Provided are a nonvolatile memory device and an operating method thereof. The nonvolatile memory device may include a conductive pillar, a resistance change layer surrounding a side surface of the conductive pillar, a semiconductor layer surrounding a side surface of the resistance change layer, a gate insulating layer surrounding a side surface of the semiconductor layer, and a plurality of insulating patterns and a plurality of gate electrodes alternately arranged along a surface of the gate insulating layer. The plurality of insulating patterns and the plurality of gate electrodes may surround a side surface of the gate insulating layer.
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