Semiconductor device including data storage material pattern

    公开(公告)号:US12232429B2

    公开(公告)日:2025-02-18

    申请号:US17384933

    申请日:2021-07-26

    Abstract: A semiconductor device includes a first conductive line on a lower structure and extending in a first horizontal direction; a second conductive line on the first conductive line and extending in a second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction; and a memory cell structure between the first conductive line and the second conductive line. The memory cell may structure include a data storage material pattern and a selector material pattern overlapping the data storage material pattern in a vertical direction. The data storage material pattern may include a phase change material layer of InαGeβSbγTeδ. In the phase change material layer of InαGeβSbγTeδ, a sum of α and β may be lower than about 30 at. %, and a sum of γ and δ may be higher than about 70 at. %.

    Variable resistance memory device

    公开(公告)号:US12185647B2

    公开(公告)日:2024-12-31

    申请号:US18119970

    申请日:2023-03-10

    Abstract: A variable resistance memory device includes a first conductive line extending on a substrate in a first horizontal direction; a second conductive line extending on the first conductive line in a second horizontal direction perpendicular to the first horizontal direction; and a memory cell at an intersection between the first conductive line and the second conductive line, the memory cell including a selection element and a variable resistor, wherein the variable resistor includes a first variable resistance layer having a senary component represented by CaGebSbcTedAeXf, in which A and X are each a group 13 element different from each other, and 1≤a≤18, 13≤b≤26, 15≤c≤30, 35≤d≤55, 0.1≤e≤8, 0.1≤f≤8, and a+b+c+d+e+f=100.

    SEMICONDUCTOR DEVICES
    6.
    发明公开

    公开(公告)号:US20230165174A1

    公开(公告)日:2023-05-25

    申请号:US17938200

    申请日:2022-10-05

    Abstract: A semiconductor device includes gate electrodes on a substrate, a channel and a resistance pattern. The gate electrodes are spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate. The channel extends through the gate electrodes in the vertical direction on the substrate. The resistance pattern includes a phase-changeable material. The resistance pattern includes a first vertical extension portion on a sidewall of the channel and extending in the vertical direction, a first protrusion portion on an inner sidewall of the first vertical extension portion and protruding in a horizontal direction substantially parallel to the upper surface of the substrate, and a second protrusion portion on an outer sidewall of the first vertical extension portion and protruding in the horizontal direction and not overlapping the first protrusion portion in the horizontal direction.

    MEMORY DEVICE INCLUDING PHASE-CHANGE MATERIAL

    公开(公告)号:US20230380195A1

    公开(公告)日:2023-11-23

    申请号:US18150123

    申请日:2023-01-04

    CPC classification number: H10B63/845 H10B63/10 H10B63/24

    Abstract: A memory device including a phase-change material includes: a substrate; a first memory cell including a first selection layer and a first phase-change material layer, and a second memory cell including a second selection layer and a second phase-change material layer, wherein the first memory cell and the second memory cell are arranged apart from each other with an insulating layer therebetween in a normal direction of the substrate, wherein the first phase-change material layer and the second phase-change material layer include: a first layer including a thermal confinement material; and a second layer including a phase-change material, respectively, wherein the first layer and the second layer extend in a direction vertical to the substrate, and wherein the first phase-change material layer is physically isolated from the second phase-change material layer by the insulating layer.

    MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20230371285A1

    公开(公告)日:2023-11-16

    申请号:US18302415

    申请日:2023-04-18

    CPC classification number: H10B63/845 H10B63/34

    Abstract: A memory device includes: a gate stack on a substrate, including insulation layers and gate electrodes alternately stacked in a vertical direction, and defining a through hole in the vertical direction; and a pillar structure in the through hole, the pillar structure including: a plurality of channel portions in the through hole to face the gate electrodes and having annular horizontal cross-sections; a plurality of conductive layers in the through hole to face the insulation layers, having annular horizontal cross-sections, and having inner walls protruding toward a center of the through hole with respect to inner walls of the channel portions; and a variable resistance material layer on the inner walls of the channel portions and the inner walls of the conductive layers, in the through hole, and a first portion of the variable resistance material layer overlaps the conductive layers in the vertical direction.

Patent Agency Ranking