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公开(公告)号:US12232429B2
公开(公告)日:2025-02-18
申请号:US17384933
申请日:2021-07-26
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jeonghee Park , Dongho Ahn , Wonjun Park
Abstract: A semiconductor device includes a first conductive line on a lower structure and extending in a first horizontal direction; a second conductive line on the first conductive line and extending in a second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction; and a memory cell structure between the first conductive line and the second conductive line. The memory cell may structure include a data storage material pattern and a selector material pattern overlapping the data storage material pattern in a vertical direction. The data storage material pattern may include a phase change material layer of InαGeβSbγTeδ. In the phase change material layer of InαGeβSbγTeδ, a sum of α and β may be lower than about 30 at. %, and a sum of γ and δ may be higher than about 70 at. %.
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公开(公告)号:US20240107778A1
公开(公告)日:2024-03-28
申请号:US18298642
申请日:2023-04-11
Applicant: Samsung Electronics Co., Ltd.
Inventor: Changseung LEE , Kiyeon Yang , Youngjae Kang , Hajun Sung , Dongho Ahn
Abstract: A phase-change memory structure includes lower and upper electrodes spaced apart from each other, and a phase-change material stack between the lower and upper electrodes. The phase-change material stack includes a plurality of phase-change layers, at least two phase-change layers of the plurality of phase-change layers have different phase-change temperatures, and a plurality of barrier layers between the plurality of phase-change layers The at least two phase-change layers of the plurality of phase-change layers have different thicknesses.
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公开(公告)号:US11744167B2
公开(公告)日:2023-08-29
申请号:US17330950
申请日:2021-05-26
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kiyeon Yang , Dongho Ahn , Changseung Lee
CPC classification number: H10N70/8828 , H10B63/24 , H10B63/84 , H10N70/066 , H10N70/231 , H10N70/8413
Abstract: Semiconductor unit devices may be arranged between a first insulating layer and a second insulating layer that are apart from each other in a direction normal to a substrate. Each of the semiconductor unit devices may include a selection device layer and a phase change material layer that extend side by side in a direction parallel to the substrate. The phase change material layer may have a superlattice-like structure. The phase change material layer may be arranged along a recess portion that is formed by the first insulating layer, the second insulating layer, and the selection device layer.
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公开(公告)号:US12185647B2
公开(公告)日:2024-12-31
申请号:US18119970
申请日:2023-03-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Wonjun Park , Chungman Kim , Dongho Ahn , Changyup Park
Abstract: A variable resistance memory device includes a first conductive line extending on a substrate in a first horizontal direction; a second conductive line extending on the first conductive line in a second horizontal direction perpendicular to the first horizontal direction; and a memory cell at an intersection between the first conductive line and the second conductive line, the memory cell including a selection element and a variable resistor, wherein the variable resistor includes a first variable resistance layer having a senary component represented by CaGebSbcTedAeXf, in which A and X are each a group 13 element different from each other, and 1≤a≤18, 13≤b≤26, 15≤c≤30, 35≤d≤55, 0.1≤e≤8, 0.1≤f≤8, and a+b+c+d+e+f=100.
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公开(公告)号:US12063793B2
公开(公告)日:2024-08-13
申请号:US17362075
申请日:2021-06-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kiyeon Yang , Bonwon Koo , Segab Kwon , Chungman Kim , Yongyoung Park , Dongho Ahn , Seunggeun Yu , Changseung Lee
CPC classification number: H10B63/24 , H01L29/24 , H10N70/245 , H10N70/826 , H10N70/8833
Abstract: Provided are a chalcogen compound having ovonic threshold switching characteristics, and a switching device, a semiconductor device, and/or a semiconductor apparatus which include the chalcogen compound. The chalcogen compound includes five or more elements and may have stable switching characteristics with a low off-current value (leakage current value). The chalcogen compound includes: selenium (Se) and tellurium (Te); a first element comprising at least one of indium (In), aluminum (Al), strontium (Sr), and calcium (Ca); and a second element including germanium (Ge) and/or tin (Sn), and may further include at least one of arsenic (As), antimony (Sb), and bismuth (Bi).
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公开(公告)号:US20230165174A1
公开(公告)日:2023-05-25
申请号:US17938200
申请日:2022-10-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Changyup Park , Dongho Ahn , Donggeon Gu , Wonjun Park , Jinwoo Lee
CPC classification number: H01L45/128 , H01L27/2454 , H01L45/06 , H01L45/124 , H01L45/144 , H01L45/1253
Abstract: A semiconductor device includes gate electrodes on a substrate, a channel and a resistance pattern. The gate electrodes are spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate. The channel extends through the gate electrodes in the vertical direction on the substrate. The resistance pattern includes a phase-changeable material. The resistance pattern includes a first vertical extension portion on a sidewall of the channel and extending in the vertical direction, a first protrusion portion on an inner sidewall of the first vertical extension portion and protruding in a horizontal direction substantially parallel to the upper surface of the substrate, and a second protrusion portion on an outer sidewall of the first vertical extension portion and protruding in the horizontal direction and not overlapping the first protrusion portion in the horizontal direction.
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公开(公告)号:US10892410B2
公开(公告)日:2021-01-12
申请号:US16459637
申请日:2019-07-02
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jeonghee Park , Jiho Park , Changyup Park , Dongho Ahn
Abstract: A variable resistance memory device may include insulating layers stacked on a substrate, a first conductive line penetrating the insulating layers, switching patterns between the insulating layers, a phase change pattern between the first conductive line and each of the switching patterns, and a capping pattern disposed between the phase change pattern and the first conductive line and disposed in a region surrounded by the phase change pattern.
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公开(公告)号:US20250107461A1
公开(公告)日:2025-03-27
申请号:US18753575
申请日:2024-06-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Changyup PARK , Young Jae Kang , DongGeon Gu , Bonwon Koo , Segab Kwon , Dongho Ahn , Changseung Lee , Yongnam Ham
Abstract: Provided are variable resistance materials and a variable resistance memory devices including the same. The variable resistance memory device includes: a first electrode; a first variable resistance material on the first electrode; and a second electrode on the first variable resistance material. The first variable resistance material includes germanium, antimony, tellurium, carbon, and sulfur and is expressed by CpSqGexSbyTez, where p is an atomic concentration of carbon, q is an atomic concentration of sulfur, x is an atomic concentration of germanium, y is an atomic concentration of antimony, and z is an atomic concentration of tellurium, wherein a sum of p, q, x, y, and z equals 1, wherein each of p, q, x, y, and z is greater than zero, and wherein q is greater than 0.01 and is less than or equal to about 0.2.
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公开(公告)号:US20230380195A1
公开(公告)日:2023-11-23
申请号:US18150123
申请日:2023-01-04
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kiyeon YANG , Changseung Lee , Dongho Ahn
CPC classification number: H10B63/845 , H10B63/10 , H10B63/24
Abstract: A memory device including a phase-change material includes: a substrate; a first memory cell including a first selection layer and a first phase-change material layer, and a second memory cell including a second selection layer and a second phase-change material layer, wherein the first memory cell and the second memory cell are arranged apart from each other with an insulating layer therebetween in a normal direction of the substrate, wherein the first phase-change material layer and the second phase-change material layer include: a first layer including a thermal confinement material; and a second layer including a phase-change material, respectively, wherein the first layer and the second layer extend in a direction vertical to the substrate, and wherein the first phase-change material layer is physically isolated from the second phase-change material layer by the insulating layer.
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公开(公告)号:US20230371285A1
公开(公告)日:2023-11-16
申请号:US18302415
申请日:2023-04-18
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jinwoo Lee , Dongho Ahn , Donggeon Gu
IPC: H10B63/00
CPC classification number: H10B63/845 , H10B63/34
Abstract: A memory device includes: a gate stack on a substrate, including insulation layers and gate electrodes alternately stacked in a vertical direction, and defining a through hole in the vertical direction; and a pillar structure in the through hole, the pillar structure including: a plurality of channel portions in the through hole to face the gate electrodes and having annular horizontal cross-sections; a plurality of conductive layers in the through hole to face the insulation layers, having annular horizontal cross-sections, and having inner walls protruding toward a center of the through hole with respect to inner walls of the channel portions; and a variable resistance material layer on the inner walls of the channel portions and the inner walls of the conductive layers, in the through hole, and a first portion of the variable resistance material layer overlaps the conductive layers in the vertical direction.
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