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公开(公告)号：US11574956B2
公开(公告)日：2023-02-07
申请号：US17314638
申请日：2021-05-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jiho Park , Kwangmin Park , Wonjun Park , Jeonghee Park , Changyup Park , Hwasung Chae
Abstract: A semiconductor device includes a substrate; first conductive lines extending in a first direction; second conductive lines extending in a second direction; memory cell structures between the first conductive lines and the second conductive lines; and dummy cell structures that are electrically isolated and between the first conductive lines and the second conductive lines. The memory cell structures include a data storage material pattern including a phase change material layer; and a selector material pattern overlapping the data storage material pattern in a vertical direction. The dummy cell structures include a dummy pattern including a phase change material layer. The phase change material layer of the dummy pattern includes a crystalline phase portion and an amorphous phase portion. At a cross section of the phase change material layer of the dummy pattern, an area of the crystalline phase portion is larger than an area of the amorphous phase portion.
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公开(公告)号：US10566530B2
公开(公告)日：2020-02-18
申请号：US16170108
申请日：2018-10-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Changyup Park , Jeonghee Park , Jaeho Jung
Abstract: Disclosed is a method of fabricating a semiconductor device. The method may include forming a mold layer on a substrate, the mold layer having a hole exposing a portion of the substrate, forming a phase transition layer with a void, in the hole, and thermally treating the phase transition layer to remove the void from the phase transition layer. The thermal treating of the phase transition layer may include heating the substrate to a first temperature to form a diffusion layer in the phase transition layer, and the first temperature may be lower than or equal to 55% of a melting point of the phase transition layer.
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公开(公告)号：US09985204B2
公开(公告)日：2018-05-29
申请号：US15451961
申请日：2017-03-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jinwoo Lee , Jeonghee Park , Dongho Ahn , Zhe Wu , Heeju Shin , Ja bin Lee
CPC classification number: H01L45/141 , H01L43/08 , H01L43/10 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/16
Abstract: A semiconductor memory device including first lines and second lines overlapping and intersecting each other, variable resistance memory elements disposed at intersections between the first lines and the second lines, and switching elements disposed between the variable resistance memory elements and the first lines. At least one of the switching elements includes first and second chalcogenide compound layers, and conductive nano-dots disposed between the first and second chalcogenide compound layers.
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公开(公告)号：US11723285B2
公开(公告)日：2023-08-08
申请号：US17655589
申请日：2022-03-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sanghoon Ahn , Oik Kwon , Jeonghee Park , Kihyun Hwang
CPC classification number: H10N50/10 , H10B61/00 , H10B63/80 , H10N50/01 , H10N50/85 , H10N70/063 , H10N70/068 , H10N70/841 , H10N70/882
Abstract: A variable resistance memory device is provided including a plurality of lower electrodes disposed on a substrate. A plurality of variable resistors are disposed on the plurality of lower electrodes. A plurality of upper electrodes are disposed on the plurality of variable resistors. An interlayer insulating layer fills a space in the plurality of variable resistors. An anti-oxidation layer is disposed between the plurality of variable resistors and the interlayer insulating layer. The anti-oxidation layer covers side surfaces of the plurality of variable resistors, and the anti-oxidation layer comprises silicon and/or carbon.
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公开(公告)号：US20220209103A1
公开(公告)日：2022-06-30
申请号：US17655589
申请日：2022-03-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SANGHOON AHN , Oik Kwon , Jeonghee Park , Kihyun Hwang
Abstract: A variable resistance memory device is provided including a plurality of lower electrodes disposed on a substrate. A plurality of variable resistors are disposed on the plurality of lower electrodes. A plurality of upper electrodes are disposed on the plurality of variable resistors. An interlayer insulating layer fills a space in the plurality of variable resistors. An anti-oxidation layer is disposed between the plurality of variable resistors and the interlayer insulating layer. The anti-oxidation layer covers side surfaces of the plurality of variable resistors, and the anti-oxidation layer comprises silicon and/or carbon.
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Patent Agency Ranking
公开(公告)号：US11127792B2
公开(公告)日：2021-09-21
申请号：US16710450
申请日：2019-12-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Si-Ho Song , Jeonghee Park , Changhyun Cho
Abstract: A three-dimensional semiconductor memory device includes first conductive lines extending horizontally in a first direction, a second conductive line extending vertically in a second direction perpendicular to the first direction, and memory cells at cross-points between the first conductive lines and the second conductive line. The first conductive lines are laterally spaced apart from each other in a third direction crossing the first direction. Each of the memory cells includes a variable resistance element and a switching element that are horizontally arranged. The variable resistance element includes a first variable resistance pattern and a second variable resistance pattern arranged in the second direction, a first electrode between the first variable resistance pattern and the first conductive line, a second electrode between the second variable resistance pattern and the second conductive line, and a third electrode between the first variable resistance pattern and the second variable resistance pattern.
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公开(公告)号：US11017989B2
公开(公告)日：2021-05-25
申请号：US16127452
申请日：2018-09-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jiho Park , Jeonghee Park , Changyup Park
Abstract: Disclosed are a collimator, a fabrication apparatus including the same, and a method of fabricating a semiconductor device using the same. The fabrication apparatus may include a chamber, a heater chuck provided in a lower region of the chamber and configured to heat a substrate, a target provided over the heater chuck, the target containing a source for a thin layer to be deposited on the substrate, a plasma electrode provided in an upper region of the chamber and configured to generate plasma near the target and thereby to produce particles from the source, and a collimator provided between the heater chuck and the target.
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8.发明申请公开(公告)号：US20180277758A1
公开(公告)日：2018-09-27
申请号：US15927481
申请日：2018-03-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jeonghee Park , Kyoung Sun Kim
IPC: H01L45/00 , H01L27/24 , C23C16/34 , C23C16/455
Abstract: A method of forming a target layer in semiconductor fabrication is disclosed that includes steps of forming a first layer by performing a first process at least one time and forming a second layer by performing a second process at least one time, wherein the first process may include supplying a first source gas, supplying a second source gas several times, and supplying an inert gas several times.
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公开(公告)号：US09893281B2
公开(公告)日：2018-02-13
申请号：US15344772
申请日：2016-11-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hideki Horii , Jeonghee Park , Sugwoo Jung
CPC classification number: H01L45/1608 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/065 , H01L45/1233 , H01L45/1253 , H01L45/1273 , H01L45/141
Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a selection element, a lower electrode pattern provided on the selection element to include a horizontal portion and a vertical portion; and a phase-changeable pattern on the lower electrode pattern. The vertical portion may extend from the horizontal portion toward the phase-changeable pattern and have a top surface, whose area is smaller than that of a bottom surface of the phase-changeable pattern.
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公开(公告)号：US08962438B2
公开(公告)日：2015-02-24
申请号：US14032997
申请日：2013-09-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jeonghee Park , Hideki Horii , Hyeyoung Park , Jin Ho Oh , Hyun-Suk Kwon
CPC classification number: H01L45/16 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/124 , H01L45/1293 , H01L45/141 , H01L45/1683
Abstract: Provided are a variable resistance memory device and a method of forming the same. The variable resistance memory device may include a substrate, a plurality of bottom electrodes on the substrate, and a first interlayer insulating layer including a trench formed therein. The trench exposes the bottom electrodes and extends in a first direction. The variable resistance memory device further includes a top electrode provided on the first interlayer insulating layer and extending in a second direction crossing the first direction and a plurality of variable resistance patterns provided in the trench and having sidewalls aligned with a sidewall of the top electrode.
Abstract translation: 提供了一种可变电阻存储器件及其形成方法。 可变电阻存储器件可以包括衬底，在衬底上的多个底部电极，以及包括形成在其中的沟槽的第一层间绝缘层。 沟槽露出底部电极并沿第一方向延伸。 可变电阻存储器件还包括设置在第一层间绝缘层上并沿与第一方向交叉的第二方向延伸的顶电极和设置在沟槽中并具有与顶电极的侧壁对准的侧壁的多个可变电阻图案。
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